sys/dev/drm/amd/amdgpu/uvd_v4_2.c

291

WREG32(mmUVD_LMI_CTRL, 0x203108);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

331

WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

748

WREG32(mmUVD_LMI_CTRL,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

873

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

988

WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1045

WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

793

tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

794

WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

990

WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,