sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

907

case mmUVD_GPCOM_VCPU_DATA1:

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

484

ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

458

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

465

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

474

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

481

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1044

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1057

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1072

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

913

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

920

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1174

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1184

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1350

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1366

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1345

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1355

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1401

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1435

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));