sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

904

case mmUVD_GPCOM_VCPU_DATA0:

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

482

ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

456

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

463

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

472

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

479

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1042

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1055

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1070

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

911

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

918

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1171

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1181

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1347

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1363

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1300

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1342

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1352

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1398

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1432

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));