sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

910

case mmUVD_GPCOM_VCPU_CMD:

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

486

ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

460

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

467

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

476

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

483

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1046

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1061

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1078

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

915

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

922

amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1177

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1187

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1353

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1372

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1303

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1319

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1348

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1358

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1407

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1438

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));