Symbol: mmSDMA0_GFX_RB_WPTR_POLL_CNTL
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
716
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
728
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
110
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
131
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
66
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
778
wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
783
WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);