sys/dev/drm/amd/amdgpu/cik_sdma.c

181

return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;

sys/dev/drm/amd/amdgpu/cik_sdma.c

195

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],

sys/dev/drm/amd/amdgpu/cik_sdma.c

468

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

484

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

207

u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

223

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

444

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

460

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

369

wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

396

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

719

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

373

lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

421

WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

715

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

735

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);