sys/dev/drm/amd/amdgpu/cik_sdma.c

314

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/cik_sdma.c

316

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

464

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

487

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

345

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

347

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

433

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

440

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

464

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

519

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

521

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

671

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

678

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

732

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

572

rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

574

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

703

rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

710

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

787

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);