sys/dev/drm/amd/amdgpu/cik_sdma.c

317

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

495

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

107

mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

246

mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

348

ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

350

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

466

ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

472

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

100

mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

119

mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

133

mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

147

mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

167

mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

522

ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

524

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

734

ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

740

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

81

mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

109

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

575

ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

577

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

65

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

789

ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

795

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);