sys/dev/drm/amd/amdgpu/cik_sdma.c

1137

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1139

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1142

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1144

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1153

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1155

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1158

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1160

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

373

f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/cik_sdma.c

388

WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1029

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1031

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1034

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1036

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1045

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1047

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1050

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1052

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1364

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1366

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1369

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1371

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1380

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1382

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1385

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1387

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

580

f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

599

WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1458

sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1459

sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

634

f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

645

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

761

temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

763

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

825

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

829

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

832

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

835

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

850

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

853

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);