sys/dev/drm/amd/amdgpu/cik_ih.c

138

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

201

tmp = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cik_ih.c

203

WREG32(mmIH_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/cik_ih.c

61

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cik_ih.c

66

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

79

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cik_ih.c

84

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

140

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

203

tmp = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cz_ih.c

205

WREG32(mmIH_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/cz_ih.c

61

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cz_ih.c

66

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

79

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/cz_ih.c

84

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

140

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

203

tmp = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/iceland_ih.c

205

WREG32(mmIH_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/iceland_ih.c

61

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/iceland_ih.c

66

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

79

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/iceland_ih.c

84

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/tonga_ih.c

136

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/tonga_ih.c

214

tmp = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/tonga_ih.c

216

WREG32(mmIH_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/tonga_ih.c

60

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/tonga_ih.c

64

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/tonga_ih.c

77

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/tonga_ih.c

81

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/vega10_ih.c

100

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

124

WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/vega10_ih.c

215

tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));

sys/dev/drm/amd/amdgpu/vega10_ih.c

217

WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);

sys/dev/drm/amd/amdgpu/vega10_ih.c

47

u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

51

WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/vega10_ih.c

64

u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

68

WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);