sys/dev/drm/amd/amdgpu/dce_v10_0.c

1112

wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1114

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1121

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1127

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1138

wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1140

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1147

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1153

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1047

wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1051

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1056

tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1059

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1064

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

117

- mmDPG_WATERMARK_MASK_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

123

- mmDPG_WATERMARK_MASK_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

129

- mmDPG_WATERMARK_MASK_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

135

- mmDPG_WATERMARK_MASK_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

141

- mmDPG_WATERMARK_MASK_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

147

- mmDPG_WATERMARK_MASK_CONTROL),