sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c

774

mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */

sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c

775

mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */

sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c

776

mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */

sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c

777

mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */

sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c

778

mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */

sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c

779

mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */

sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c

780

mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */

sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c

838

mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];