sys/dev/drm/amd/amdgpu/dce_v10_0.c

3017

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3019

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3022

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3024

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

306

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

311

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3167

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3169

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

341

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

343

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3143

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3145

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3148

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3150

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

324

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

329

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3293

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3295

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

359

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

361

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);