sys/dev/drm/amd/amdgpu/cik.c

901

d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/cik.c

911

WREG32(mmD1VGA_CONTROL,

sys/dev/drm/amd/amdgpu/cik.c

927

WREG32(mmD1VGA_CONTROL, d1vga_control);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1788

mmD1VGA_CONTROL,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1830

mmD1VGA_CONTROL,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1717

mmD1VGA_CONTROL,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

963

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1081

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

882

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/vi.c

385

d1vga_control = RREG32(mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/vi.c

395

WREG32(mmD1VGA_CONTROL,

sys/dev/drm/amd/amdgpu/vi.c

411

WREG32(mmD1VGA_CONTROL, d1vga_control);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1807

addr = mmD1VGA_CONTROL;

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

413

offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL;

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

416

offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL;

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

419

offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL;

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

422

offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

425

offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

431

value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

439

dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);