sys/dev/drm/amd/amdgpu/dce_v10_0.c

407

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

478

crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),

sys/dev/drm/amd/amdgpu/dce_v10_0.c

482

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

484

WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

423

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

504

crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),

sys/dev/drm/amd/amdgpu/dce_v11_0.c

508

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

510

WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

341

if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {

sys/dev/drm/amd/amdgpu/dce_v8_0.c

418

crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),

sys/dev/drm/amd/amdgpu/dce_v8_0.c

422

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

424

WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

109

.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

113

.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

117

.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

121

.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

125

.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

129

.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

118

.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

122

.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

126

.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

130

.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

134

.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

138

.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

111

uint32_t address = CRTC_REG(mmCRTC_CONTROL);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

2087

addr = CRTC_REG(mmCRTC_CONTROL);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

590

uint32_t address = mmCRTC_CONTROL;

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

120

.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

124

.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

128

.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

132

.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

136

.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

140

.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

114

.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

120

.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

126

.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

132

.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

138

.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

144

.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),