sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

345

for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

346

WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

360

WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

412

for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

433

hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

517

for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3033

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3036

for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3037

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4664

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4678

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4681

for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4682

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3059

WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,

sys/dev/drm/amd/powerplay/inc/polaris10_pwrvirus.h

1505

{ 0x54116f00, mmCP_MQD_BASE_ADDR },

sys/dev/drm/amd/powerplay/inc/polaris10_pwrvirus.h

1515

{ 0x54117300, mmCP_MQD_BASE_ADDR },

sys/dev/drm/amd/powerplay/inc/polaris10_pwrvirus.h

1525

{ 0x54117700, mmCP_MQD_BASE_ADDR },

sys/dev/drm/amd/powerplay/inc/polaris10_pwrvirus.h

1535

{ 0x54117b00, mmCP_MQD_BASE_ADDR },