sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

367

WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

443

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2915

RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2970

RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4535

tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4585

tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2914

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2982

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3037

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3098

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3153

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3154

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);