Symbol: mmBIF_BX_PF0_MAILBOX_CONTROL
sys/dev/drm/amd/amdgpu/mxgpu_ai.h
56
#define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4
sys/dev/drm/amd/amdgpu/mxgpu_ai.h
57
#define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1