mipi_config
struct mipi_config *config;
const struct mipi_config *config;
dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
intel_dsi->lane_count = mipi_config->lane_cnt + 1;
mipi_config->videomode_color_format << 7);
intel_dsi->dual_link = mipi_config->dual_link;
intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
intel_dsi->operation_mode = mipi_config->is_cmd_mode;
intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
intel_dsi->init_count = mipi_config->master_init_timer;
intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
if (mipi_config->target_burst_mode_freq) {
if (mipi_config->target_burst_mode_freq <
mipi_config->target_burst_mode_freq * 100,
tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
ths_prepare_hszero = mipi_config->ths_prepare_hszero;
ths_prepare_ns = max(mipi_config->ths_prepare,
mipi_config->tclk_prepare);
tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
struct mipi_config config[MAX_MIPI_CONFIGURATIONS];