sys/bus/u4b/uvc/uvc_buf.c

107

uint64_t max_offset = (uint64_t)(bq->buf_size * bq->buf_count) - PAGE_SIZE;

sys/bus/u4b/uvc/uvc_buf.c

115

if (max_offset < 0)

sys/bus/u4b/uvc/uvc_buf.c

118

if (offset > max_offset) {

sys/bus/u4b/uvc/uvc_buf.c

122

max_offset);

sys/dev/drm/amd/amdgpu/amdgpu_object.c

852

u64 min_offset, u64 max_offset)

sys/dev/drm/amd/amdgpu/amdgpu_object.c

861

if (WARN_ON_ONCE(min_offset > max_offset))

sys/dev/drm/amd/amdgpu/amdgpu_object.c

885

if (max_offset != 0) {

sys/dev/drm/amd/amdgpu/amdgpu_object.c

887

WARN_ON_ONCE(max_offset <

sys/dev/drm/amd/amdgpu/amdgpu_object.c

903

lpfn = max_offset >> PAGE_SHIFT;

sys/dev/drm/amd/amdgpu/amdgpu_object.h

248

u64 min_offset, u64 max_offset);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3982

int max_offset)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3993

BUG_ON(*offset_count >= max_offset);

sys/dev/drm/radeon/radeon_object.c

324

int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,

sys/dev/drm/radeon/radeon_object.c

338

if (max_offset != 0) {

sys/dev/drm/radeon/radeon_object.c

345

WARN_ON_ONCE(max_offset <

sys/dev/drm/radeon/radeon_object.c

361

(!max_offset || max_offset > bo->rdev->mc.visible_vram_size))

sys/dev/drm/radeon/radeon_object.c

365

bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;

sys/dev/drm/radeon/radeon_object.h

137

u64 max_offset, u64 *gpu_addr);

sys/dev/video/cxm/cxm_tuner.c

809

unsigned long max_offset;

sys/dev/video/cxm/cxm_tuner.c

821

max_offset = 2000;

sys/dev/video/cxm/cxm_tuner.c

824

for (i = 0; i < (max_offset / step_size); i++) {