sys/dev/drm/amd/amdgpu/ci_dpm.c

664

data = RREG32_DIDT(ixDIDT_DB_CTRL0);

sys/dev/drm/amd/amdgpu/ci_dpm.c

669

WREG32_DIDT(ixDIDT_DB_CTRL0, data);

sys/dev/drm/amd/amdgpu/kv_dpm.c

475

data = RREG32_DIDT(ixDIDT_DB_CTRL0);

sys/dev/drm/amd/amdgpu/kv_dpm.c

480

WREG32_DIDT(ixDIDT_DB_CTRL0, data);

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

247

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

248

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

249

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

250

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

251

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

252

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

253

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

254

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

255

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

256

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },

sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c

257

{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },