sys/dev/drm/i915/intel_crt.c

226

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

sys/dev/drm/i915/intel_crt.c

246

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);

sys/dev/drm/i915/intel_crt.c

257

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

sys/dev/drm/i915/intel_crt.c

292

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);

sys/dev/drm/i915/intel_display.c

13451

intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);

sys/dev/drm/i915/intel_display.c

5648

intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

5714

intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

5902

intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

5943

intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_dp.c

3866

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

sys/dev/drm/i915/intel_dp.c

3881

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);

sys/dev/drm/i915/intel_dp.c

4411

intel_set_pch_fifo_underrun_reporting(dev_priv,

sys/dev/drm/i915/intel_dp.c

4422

intel_set_pch_fifo_underrun_reporting(dev_priv,

sys/dev/drm/i915/intel_drv.h

1373

bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_fifo_underrun.c

397

if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,

sys/dev/drm/i915/intel_hdmi.c

1419

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

sys/dev/drm/i915/intel_hdmi.c

1438

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);

sys/dev/drm/i915/intel_sdvo.c

1559

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

sys/dev/drm/i915/intel_sdvo.c

1570

intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);