sys/dev/drm/radeon/evergreen.c

1186

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

sys/dev/drm/radeon/evergreen.c

1190

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

sys/dev/drm/radeon/evergreen.c

1201

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

sys/dev/drm/radeon/evergreen.c

1204

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

sys/dev/drm/radeon/evergreen.c

1205

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

sys/dev/drm/radeon/evergreen.c

1208

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/evergreen.c

1212

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

sys/dev/drm/radeon/evergreen.c

1217

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/evergreen.c

1226

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

sys/dev/drm/radeon/evergreen.c

1242

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/evergreen.c

1247

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

sys/dev/drm/radeon/evergreen.c

1249

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

sys/dev/drm/radeon/r600.c

204

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(

sys/dev/drm/radeon/r600.c

213

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

sys/dev/drm/radeon/r600.c

233

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

sys/dev/drm/radeon/r600.c

238

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/r600.c

242

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,

sys/dev/drm/radeon/r600.c

246

WREG32_P(CG_UPLL_FUNC_CNTL,

sys/dev/drm/radeon/r600.c

262

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/r600.c

267

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

sys/dev/drm/radeon/r600.c

272

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

sys/dev/drm/radeon/rv770.c

107

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/rv770.c

112

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

sys/dev/drm/radeon/rv770.c

115

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

sys/dev/drm/radeon/rv770.c

60

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

sys/dev/drm/radeon/rv770.c

78

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));

sys/dev/drm/radeon/rv770.c

81

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

sys/dev/drm/radeon/rv770.c

84

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

sys/dev/drm/radeon/rv770.c

89

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/rv770.c

92

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);

sys/dev/drm/radeon/si.c

7003

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

sys/dev/drm/radeon/si.c

7020

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

sys/dev/drm/radeon/si.c

7023

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

sys/dev/drm/radeon/si.c

7026

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/si.c

7030

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

sys/dev/drm/radeon/si.c

7035

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/si.c

7044

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

sys/dev/drm/radeon/si.c

7060

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

sys/dev/drm/radeon/si.c

7065

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

sys/dev/drm/radeon/si.c

7067

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);