sys/dev/drm/amd/amdgpu/si_dpm.c

4030

si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1414

CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1416

CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

325

spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

327

spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1347

spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1349

spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

887

spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

889

spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1462

CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1464

CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

826

CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

828

CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1210

spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1212

spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

568

CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

570

CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);

sys/dev/drm/radeon/ci_dpm.c

1909

RREG32_SMC(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/ni_dpm.c

1183

ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/r600_dpm.c

323

WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);

sys/dev/drm/radeon/r600_dpm.c

325

WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);

sys/dev/drm/radeon/r600_dpm.c

333

if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)

sys/dev/drm/radeon/rs780_dpm.c

1008

u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/rs780_dpm.c

211

u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;

sys/dev/drm/radeon/rs780_dpm.c

986

u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/rv730_dpm.c

203

RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/rv740_dpm.c

294

RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/rv770_dpm.c

1526

RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/si.c

3977

tmp = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/si.c

3979

WREG32(CG_SPLL_FUNC_CNTL, tmp);

sys/dev/drm/radeon/si.c

4008

tmp = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/si.c

4010

WREG32(CG_SPLL_FUNC_CNTL, tmp);

sys/dev/drm/radeon/si.c

4012

tmp = RREG32(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/si.c

4014

WREG32(CG_SPLL_FUNC_CNTL, tmp);

sys/dev/drm/radeon/si_dpm.c

3574

si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);