sys/dev/drm/amd/amdgpu/si_dpm.c

4151

tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);

sys/dev/drm/amd/amdgpu/si_dpm.c

4162

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

4265

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/amd/amdgpu/si_dpm.c

4274

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

389

display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

392

display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4048

display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);

sys/dev/drm/radeon/ci_dpm.c

2021

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/ci_dpm.c

2033

WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/ci_dpm.c

2082

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/ci_dpm.c

2088

WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/cypress_dpm.c

1734

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/cypress_dpm.c

1743

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/cypress_dpm.c

1751

tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);

sys/dev/drm/radeon/cypress_dpm.c

1762

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/rv6xx_dpm.c

1183

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/rv6xx_dpm.c

1196

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/rv6xx_dpm.c

990

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/rv770_dpm.c

1348

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/rv770_dpm.c

1361

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/rv770_dpm.c

884

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/rv770_dpm.c

889

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/si_dpm.c

3689

tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);

sys/dev/drm/radeon/si_dpm.c

3700

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/si_dpm.c

3803

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/si_dpm.c

3812

WREG32(CG_DISPLAY_GAP_CNTL, tmp);