sys/dev/drm/i915/intel_lrc.c

1465

*batch++ = i915_scratch_offset(engine->i915) + 256;

sys/dev/drm/i915/intel_lrc.c

1479

*batch++ = i915_scratch_offset(engine->i915) + 256;

sys/dev/drm/i915/intel_lrc.c

1516

i915_scratch_offset(engine->i915) +

sys/dev/drm/i915/intel_lrc.c

1593

i915_scratch_offset(engine->i915)

sys/dev/drm/i915/intel_lrc.c

2163

i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;

sys/dev/drm/i915/intel_ringbuffer.c

1550

*cs++ = i915_scratch_offset(rq->i915);

sys/dev/drm/i915/intel_ringbuffer.c

162

*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;

sys/dev/drm/i915/intel_ringbuffer.c

1659

*cs++ = i915_scratch_offset(rq->i915);

sys/dev/drm/i915/intel_ringbuffer.c

170

*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;

sys/dev/drm/i915/intel_ringbuffer.c

222

u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;

sys/dev/drm/i915/intel_ringbuffer.c

255

u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;

sys/dev/drm/i915/intel_ringbuffer.c

324

u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;

sys/dev/drm/i915/intel_ringbuffer.c

89

*cs++ = i915_scratch_offset(rq->i915);

sys/dev/drm/i915/intel_ringbuffer.c

987

u32 *cs, cs_offset = i915_scratch_offset(rq->i915);