sys/dev/drm/i915/dvo.h

35

i915_reg_t dvo_reg;

sys/dev/drm/i915/dvo.h

36

i915_reg_t dvo_srcdim_reg;

sys/dev/drm/i915/gvt/gvt.h

203

i915_reg_t offset;

sys/dev/drm/i915/i915_cmd_parser.c

512

i915_reg_t addr;

sys/dev/drm/i915/i915_drv.h

1358

i915_reg_t addr;

sys/dev/drm/i915/i915_drv.h

3597

const i915_reg_t reg);

sys/dev/drm/i915/i915_drv.h

3602

const i915_reg_t reg)

sys/dev/drm/i915/i915_drv.h

3651

i915_reg_t reg) \

sys/dev/drm/i915/i915_drv.h

3658

i915_reg_t reg, uint##x##_t val) \

sys/dev/drm/i915/i915_drv.h

3711

static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/i915_drv.h

472

i915_reg_t mmioaddr[8];

sys/dev/drm/i915/i915_drv.h

672

i915_reg_t gpio_reg;

sys/dev/drm/i915/i915_drv.h

881

i915_reg_t bios;

sys/dev/drm/i915/i915_drv.h

882

i915_reg_t driver;

sys/dev/drm/i915/i915_drv.h

883

i915_reg_t kvmr;

sys/dev/drm/i915/i915_drv.h

884

i915_reg_t debug;

sys/dev/drm/i915/i915_gem_fence_reg.c

149

i915_reg_t reg = FENCE_REG(fence->id);

sys/dev/drm/i915/i915_gem_fence_reg.c

181

i915_reg_t reg = FENCE_REG(fence->id);

sys/dev/drm/i915/i915_gem_fence_reg.c

63

i915_reg_t fence_reg_lo, fence_reg_hi;

sys/dev/drm/i915/i915_gpu_error.c

1246

i915_reg_t mmio;

sys/dev/drm/i915/i915_irq.c

1397

i915_reg_t reg;

sys/dev/drm/i915/i915_irq.c

169

i915_reg_t reg)

sys/dev/drm/i915/i915_irq.c

185

i915_reg_t reg)

sys/dev/drm/i915/i915_irq.c

1887

i915_reg_t reg;

sys/dev/drm/i915/i915_irq.c

360

static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/i915_irq.c

367

static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/i915_irq.c

377

static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/i915_irq.c

437

i915_reg_t reg = gen6_pm_iir(dev_priv);

sys/dev/drm/i915/i915_irq.c

707

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/i915_irq.c

730

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/i915_irq.c

825

i915_reg_t high_frame, low_frame;

sys/dev/drm/i915/i915_perf.c

1643

i915_reg_t flex_regs[] = {

sys/dev/drm/i915/i915_perf.c

2967

static const i915_reg_t flex_eu_regs[] = {

sys/dev/drm/i915/i915_reg.h

123

#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })

sys/dev/drm/i915/i915_reg.h

127

static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)

sys/dev/drm/i915/i915_reg.h

132

static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)

sys/dev/drm/i915/i915_reg.h

137

static inline bool i915_mmio_reg_valid(i915_reg_t reg)

sys/dev/drm/i915/i915_sysfs.c

44

i915_reg_t reg)

sys/dev/drm/i915/intel_audio.c

228

i915_reg_t reg_eldv, u32 bits_eldv,

sys/dev/drm/i915/intel_audio.c

229

i915_reg_t reg_elda, u32 bits_elda,

sys/dev/drm/i915/intel_audio.c

230

i915_reg_t reg_edid)

sys/dev/drm/i915/intel_audio.c

508

i915_reg_t aud_config, aud_cntrl_st2;

sys/dev/drm/i915/intel_audio.c

557

i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;

sys/dev/drm/i915/intel_crt.c

53

i915_reg_t adpa_reg;

sys/dev/drm/i915/intel_crt.c

639

i915_reg_t bclrpat_reg, vtotal_reg,

sys/dev/drm/i915/intel_crt.c

67

i915_reg_t adpa_reg, enum i915_pipe *pipe)

sys/dev/drm/i915/intel_crt.c

933

i915_reg_t adpa_reg;

sys/dev/drm/i915/intel_ddi.c

1030

i915_reg_t reg = DDI_BUF_CTL(port);

sys/dev/drm/i915/intel_ddi.c

1273

i915_reg_t reg)

sys/dev/drm/i915/intel_ddi.c

1309

i915_reg_t cfgcr1_reg, cfgcr2_reg;

sys/dev/drm/i915/intel_ddi.c

1897

i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

1048

i915_reg_t reg = PIPEDSL(pipe);

sys/dev/drm/i915/intel_display.c

1093

i915_reg_t reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

1204

i915_reg_t pp_reg;

sys/dev/drm/i915/intel_display.c

1331

i915_reg_t dp_reg)

sys/dev/drm/i915/intel_display.c

1349

i915_reg_t hdmi_reg)

sys/dev/drm/i915/intel_display.c

1512

i915_reg_t reg = DPLL(crtc->pipe);

sys/dev/drm/i915/intel_display.c

15150

i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);

sys/dev/drm/i915/intel_display.c

15636

i915_reg_t reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

15775

i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);

sys/dev/drm/i915/intel_display.c

1641

i915_reg_t dpll_reg;

sys/dev/drm/i915/intel_display.c

1674

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

1762

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

1826

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

1882

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

3402

i915_reg_t reg = DSPCNTR(i9xx_plane);

sys/dev/drm/i915/intel_display.c

3953

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

3996

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4097

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4230

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4348

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4385

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4416

i915_reg_t reg;

sys/dev/drm/i915/intel_display.c

4782

i915_reg_t reg = TRANS_DP_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4827

i915_reg_t dslreg = PIPEDSL(pipe);

sys/dev/drm/i915/intel_display.c

5922

i915_reg_t reg;

sys/dev/drm/i915/intel_dp.c

1000

i915_reg_t pp_stat;

sys/dev/drm/i915/intel_dp.c

1001

i915_reg_t pp_on;

sys/dev/drm/i915/intel_dp.c

1002

i915_reg_t pp_off;

sys/dev/drm/i915/intel_dp.c

1003

i915_reg_t pp_div;

sys/dev/drm/i915/intel_dp.c

1028

static i915_reg_t

sys/dev/drm/i915/intel_dp.c

1038

static i915_reg_t

sys/dev/drm/i915/intel_dp.c

1067

i915_reg_t pp_ctrl_reg, pp_div_reg;

sys/dev/drm/i915/intel_dp.c

1132

i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);

sys/dev/drm/i915/intel_dp.c

1266

i915_reg_t ch_ctl, ch_data[5];

sys/dev/drm/i915/intel_dp.c

1580

static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)

sys/dev/drm/i915/intel_dp.c

1596

static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)

sys/dev/drm/i915/intel_dp.c

1612

static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)

sys/dev/drm/i915/intel_dp.c

1630

static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)

sys/dev/drm/i915/intel_dp.c

1648

static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)

sys/dev/drm/i915/intel_dp.c

1667

static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)

sys/dev/drm/i915/intel_dp.c

2232

i915_reg_t pp_stat_reg, pp_ctrl_reg;

sys/dev/drm/i915/intel_dp.c

2331

i915_reg_t pp_stat_reg, pp_ctrl_reg;

sys/dev/drm/i915/intel_dp.c

2403

i915_reg_t pp_stat_reg, pp_ctrl_reg;

sys/dev/drm/i915/intel_dp.c

2487

i915_reg_t pp_ctrl_reg;

sys/dev/drm/i915/intel_dp.c

2545

i915_reg_t pp_ctrl_reg;

sys/dev/drm/i915/intel_dp.c

2593

i915_reg_t pp_ctrl_reg;

sys/dev/drm/i915/intel_dp.c

2636

i915_reg_t pp_ctrl_reg;

sys/dev/drm/i915/intel_dp.c

2857

i915_reg_t dp_reg, enum port port,

sys/dev/drm/i915/intel_dp.c

297

i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };

sys/dev/drm/i915/intel_dp.c

3248

i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);

sys/dev/drm/i915/intel_dp.c

330

i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };

sys/dev/drm/i915/intel_dp.c

6116

i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);

sys/dev/drm/i915/intel_dp.c

6680

i915_reg_t output_reg,

sys/dev/drm/i915/intel_dp.c

999

i915_reg_t pp_ctrl;

sys/dev/drm/i915/intel_dpio_phy.c

489

i915_reg_t reg, u32 mask, u32 expected,

sys/dev/drm/i915/intel_dpll_mgr.c

2933

static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)

sys/dev/drm/i915/intel_dpll_mgr.c

3092

i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);

sys/dev/drm/i915/intel_dpll_mgr.c

3144

i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);

sys/dev/drm/i915/intel_dpll_mgr.c

897

i915_reg_t ctl, cfgcr1, cfgcr2;

sys/dev/drm/i915/intel_drv.h

1026

i915_reg_t hdmi_reg;

sys/dev/drm/i915/intel_drv.h

1078

i915_reg_t output_reg;

sys/dev/drm/i915/intel_drv.h

1162

i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);

sys/dev/drm/i915/intel_drv.h

1163

i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);

sys/dev/drm/i915/intel_drv.h

1421

i915_reg_t adpa_reg, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

1697

i915_reg_t dp_reg, enum port port,

sys/dev/drm/i915/intel_drv.h

1699

bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,

sys/dev/drm/i915/intel_drv.h

1861

void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,

sys/dev/drm/i915/intel_drv.h

1879

i915_reg_t lvds_reg, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

2131

i915_reg_t sdvo_reg, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

2133

i915_reg_t reg, enum port port);

sys/dev/drm/i915/intel_dvo.c

181

i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;

sys/dev/drm/i915/intel_dvo.c

195

i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;

sys/dev/drm/i915/intel_dvo.c

272

i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;

sys/dev/drm/i915/intel_dvo.c

273

i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;

sys/dev/drm/i915/intel_dvo.c

393

static enum port intel_dvo_port(i915_reg_t dvo_reg)

sys/dev/drm/i915/intel_engine_cs.c

719

const i915_reg_t mode = RING_MI_MODE(base);

sys/dev/drm/i915/intel_engine_cs.c

786

int subslice, i915_reg_t reg)

sys/dev/drm/i915/intel_fifo_underrun.c

111

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

90

i915_reg_t reg = PIPESTAT(crtc->pipe);

sys/dev/drm/i915/intel_guc.c

41

static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)

sys/dev/drm/i915/intel_hdmi.c

130

static i915_reg_t

sys/dev/drm/i915/intel_hdmi.c

215

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

2417

i915_reg_t hdmi_reg, enum port port)

sys/dev/drm/i915/intel_hdmi.c

252

i915_reg_t reg = TVIDEO_DIP_CTL(pipe);

sys/dev/drm/i915/intel_hdmi.c

275

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

333

i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

392

i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);

sys/dev/drm/i915/intel_hdmi.c

550

i915_reg_t reg = VIDEO_DIP_CTL;

sys/dev/drm/i915/intel_hdmi.c

666

i915_reg_t reg;

sys/dev/drm/i915/intel_hdmi.c

701

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

753

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

797

i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

847

i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);

sys/dev/drm/i915/intel_lrc.c

1535

i915_reg_t reg;

sys/dev/drm/i915/intel_lvds.c

68

i915_reg_t reg;

sys/dev/drm/i915/intel_lvds.c

870

i915_reg_t lvds_reg;

sys/dev/drm/i915/intel_lvds.c

88

i915_reg_t lvds_reg, enum i915_pipe *pipe)

sys/dev/drm/i915/intel_mocs.c

208

static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)

sys/dev/drm/i915/intel_pm.c

5013

i915_reg_t reg,

sys/dev/drm/i915/intel_pm.c

5023

i915_reg_t reg,

sys/dev/drm/i915/intel_pm.c

5625

static const i915_reg_t wm0_pipe_reg[] = {

sys/dev/drm/i915/intel_pm.c

9732

const i915_reg_t reg)

sys/dev/drm/i915/intel_pm.c

9778

const i915_reg_t reg)

sys/dev/drm/i915/intel_psr.c

665

i915_reg_t psr_status;

sys/dev/drm/i915/intel_psr.c

787

i915_reg_t reg;

sys/dev/drm/i915/intel_ringbuffer.c

1643

i915_reg_t last_reg = {}; /* keep gcc quiet */

sys/dev/drm/i915/intel_ringbuffer.c

2132

i915_reg_t mbox_reg;

sys/dev/drm/i915/intel_ringbuffer.c

2156

i915_reg_t mbox_reg;

sys/dev/drm/i915/intel_ringbuffer.c

399

i915_reg_t mmio;

sys/dev/drm/i915/intel_ringbuffer.c

449

i915_reg_t reg = RING_INSTPM(engine->mmio_base);

sys/dev/drm/i915/intel_ringbuffer.c

719

i915_reg_t mbox_reg;

sys/dev/drm/i915/intel_ringbuffer.h

561

i915_reg_t signal[GEN6_NUM_SEMAPHORES];

sys/dev/drm/i915/intel_runtime_pm.c

3140

i915_reg_t reg, bool enable)

sys/dev/drm/i915/intel_sdvo.c

1405

i915_reg_t sdvo_reg, enum i915_pipe *pipe)

sys/dev/drm/i915/intel_sdvo.c

3053

i915_reg_t sdvo_reg, enum port port)

sys/dev/drm/i915/intel_sdvo.c

77

i915_reg_t sdvo_reg;

sys/dev/drm/i915/intel_uncore.c

1086

const i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.c

1100

const i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.c

1120

gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1128

gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1194

func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1234

gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1242

gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1276

gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1286

func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \

sys/dev/drm/i915/intel_uncore.c

1337

i915_reg_t reg_set,

sys/dev/drm/i915/intel_uncore.c

1338

i915_reg_t reg_ack)

sys/dev/drm/i915/intel_uncore.c

1656

i915_reg_t offset_ldw;

sys/dev/drm/i915/intel_uncore.c

1657

i915_reg_t offset_udw;

sys/dev/drm/i915/intel_uncore.c

2005

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.c

2053

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.c

2312

i915_reg_t reg)

sys/dev/drm/i915/intel_uncore.c

2335

i915_reg_t reg)

sys/dev/drm/i915/intel_uncore.c

2374

i915_reg_t reg, unsigned int op)

sys/dev/drm/i915/intel_uncore.c

912

static const i915_reg_t gen8_shadowed_regs[] = {

sys/dev/drm/i915/intel_uncore.c

922

static const i915_reg_t gen11_shadowed_regs[] = {

sys/dev/drm/i915/intel_uncore.c

936

static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)

sys/dev/drm/i915/intel_uncore.c

951

const i915_reg_t *regs = gen##x##_shadowed_regs; \

sys/dev/drm/i915/intel_uncore.h

119

i915_reg_t reg_set;

sys/dev/drm/i915/intel_uncore.h

120

i915_reg_t reg_ack;

sys/dev/drm/i915/intel_uncore.h

160

i915_reg_t reg, unsigned int op);

sys/dev/drm/i915/intel_uncore.h

180

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.h

188

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.h

197

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.h

205

i915_reg_t reg,

sys/dev/drm/i915/intel_uncore.h

71

i915_reg_t r, bool trace);

sys/dev/drm/i915/intel_uncore.h

73

i915_reg_t r, bool trace);

sys/dev/drm/i915/intel_uncore.h

75

i915_reg_t r, bool trace);

sys/dev/drm/i915/intel_uncore.h

77

i915_reg_t r, bool trace);

sys/dev/drm/i915/intel_uncore.h

80

i915_reg_t r, u8 val, bool trace);

sys/dev/drm/i915/intel_uncore.h

82

i915_reg_t r, u16 val, bool trace);

sys/dev/drm/i915/intel_uncore.h

84

i915_reg_t r, u32 val, bool trace);

sys/dev/drm/i915/intel_wopcm.c

220

i915_reg_t reg, u32 val, u32 mask,

sys/dev/drm/i915/intel_workarounds.c

624

wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

636

wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,

sys/dev/drm/i915/intel_workarounds.c

649

wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

655

wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

sys/dev/drm/i915/intel_workarounds.c

66

i915_reg_t reg, const u32 mask, const u32 val)

sys/dev/drm/i915/intel_workarounds.c

986

i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];

sys/dev/drm/i915/intel_workarounds.c

991

static void whitelist_reg(struct whitelist *w, i915_reg_t reg)

sys/dev/drm/i915/intel_workarounds.h

13

i915_reg_t reg;

sys/dev/drm/i915/vlv_dsi.c

1042

i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?

sys/dev/drm/i915/vlv_dsi.c

105

i915_reg_t reg,

sys/dev/drm/i915/vlv_dsi.c

128

i915_reg_t data_reg, ctrl_reg;

sys/dev/drm/i915/vlv_dsi.c

636

i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?

sys/dev/drm/i915/vlv_dsi.c

700

i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?

sys/dev/drm/i915/vlv_dsi.c

733

i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?

sys/dev/drm/i915/vlv_dsi.c

89

i915_reg_t reg,