sys/dev/drm/i915/i915_cmd_parser.c

1018

int ret = addr - i915_mmio_reg_offset(table[mid].addr);

sys/dev/drm/i915/i915_cmd_parser.c

755

u32 curr = i915_mmio_reg_offset(reg_table[i].addr);

sys/dev/drm/i915/i915_drv.h

3653

return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \

sys/dev/drm/i915/i915_drv.h

3660

write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \

sys/dev/drm/i915/i915_gem_execbuffer.c

1924

*cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));

sys/dev/drm/i915/i915_irq.c

177

i915_mmio_reg_offset(reg), val);

sys/dev/drm/i915/i915_irq.c

193

i915_mmio_reg_offset(reg), val);

sys/dev/drm/i915/i915_perf.c

1661

u32 mmio = i915_mmio_reg_offset(flex_regs[i]);

sys/dev/drm/i915/i915_perf.c

1674

if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {

sys/dev/drm/i915/i915_perf.c

2979

if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)

sys/dev/drm/i915/i915_perf.c

2987

return (addr >= i915_mmio_reg_offset(OASTARTTRIG1) &&

sys/dev/drm/i915/i915_perf.c

2988

addr <= i915_mmio_reg_offset(OASTARTTRIG8)) ||

sys/dev/drm/i915/i915_perf.c

2989

(addr >= i915_mmio_reg_offset(OAREPORTTRIG1) &&

sys/dev/drm/i915/i915_perf.c

2990

addr <= i915_mmio_reg_offset(OAREPORTTRIG8)) ||

sys/dev/drm/i915/i915_perf.c

2991

(addr >= i915_mmio_reg_offset(OACEC0_0) &&

sys/dev/drm/i915/i915_perf.c

2992

addr <= i915_mmio_reg_offset(OACEC7_1));

sys/dev/drm/i915/i915_perf.c

2997

return addr == i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) ||

sys/dev/drm/i915/i915_perf.c

2998

(addr >= i915_mmio_reg_offset(MICRO_BP0_0) &&

sys/dev/drm/i915/i915_perf.c

2999

addr <= i915_mmio_reg_offset(NOA_WRITE)) ||

sys/dev/drm/i915/i915_perf.c

3000

(addr >= i915_mmio_reg_offset(OA_PERFCNT1_LO) &&

sys/dev/drm/i915/i915_perf.c

3001

addr <= i915_mmio_reg_offset(OA_PERFCNT2_HI)) ||

sys/dev/drm/i915/i915_perf.c

3002

(addr >= i915_mmio_reg_offset(OA_PERFMATRIX_LO) &&

sys/dev/drm/i915/i915_perf.c

3003

addr <= i915_mmio_reg_offset(OA_PERFMATRIX_HI));

sys/dev/drm/i915/i915_perf.c

3009

addr == i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) ||

sys/dev/drm/i915/i915_perf.c

3010

(addr >= i915_mmio_reg_offset(RPM_CONFIG0) &&

sys/dev/drm/i915/i915_perf.c

3011

addr <= i915_mmio_reg_offset(NOA_CONFIG(8)));

sys/dev/drm/i915/i915_perf.c

3017

(addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) &&

sys/dev/drm/i915/i915_perf.c

3018

addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI));

sys/dev/drm/i915/i915_perf.c

3025

(addr >= i915_mmio_reg_offset(HSW_MBVID2_NOA0) &&

sys/dev/drm/i915/i915_perf.c

3026

addr <= i915_mmio_reg_offset(HSW_MBVID2_NOA9)) ||

sys/dev/drm/i915/i915_perf.c

3027

addr == i915_mmio_reg_offset(HSW_MBVID2_MISR0);

sys/dev/drm/i915/i915_perf.c

3042

if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg)

sys/dev/drm/i915/i915_perf.c

3049

if (i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) == reg)

sys/dev/drm/i915/i915_reg.h

134

return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);

sys/dev/drm/i915/intel_guc.c

56

guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));

sys/dev/drm/i915/intel_lrc.c

1464

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/drm/i915/intel_lrc.c

1469

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/drm/i915/intel_lrc.c

1478

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/drm/i915/intel_lrc.c

1545

*batch++ = i915_mmio_reg_offset(lri->reg);

sys/dev/drm/i915/intel_lrc.c

2038

*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));

sys/dev/drm/i915/intel_lrc.c

2040

*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));

sys/dev/drm/i915/intel_lrc.c

2436

i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));

sys/dev/drm/i915/intel_lrc.c

2438

i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));

sys/dev/drm/i915/intel_lrc.c

2441

i915_mmio_reg_offset(RING_ELSP(engine));

sys/dev/drm/i915/intel_lrc.c

2454

i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));

sys/dev/drm/i915/intel_lrc.c

2457

(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));

sys/dev/drm/i915/intel_lrc_reg.h

45

(reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \

sys/dev/drm/i915/intel_mocs.c

291

*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));

sys/dev/drm/i915/intel_mocs.c

304

*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));

sys/dev/drm/i915/intel_mocs.c

349

*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));

sys/dev/drm/i915/intel_mocs.c

355

*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));

sys/dev/drm/i915/intel_mocs.c

366

*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));

sys/dev/drm/i915/intel_pm.c

9796

i = (i915_mmio_reg_offset(reg) -

sys/dev/drm/i915/intel_pm.c

9797

i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);

sys/dev/drm/i915/intel_ringbuffer.c

1526

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));

sys/dev/drm/i915/intel_ringbuffer.c

1530

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));

sys/dev/drm/i915/intel_ringbuffer.c

1549

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));

sys/dev/drm/i915/intel_ringbuffer.c

1603

*cs++ = i915_mmio_reg_offset(

sys/dev/drm/i915/intel_ringbuffer.c

1651

*cs++ = i915_mmio_reg_offset(last_reg);

sys/dev/drm/i915/intel_ringbuffer.c

1658

*cs++ = i915_mmio_reg_offset(last_reg);

sys/dev/drm/i915/intel_ringbuffer.c

1689

*cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));

sys/dev/drm/i915/intel_ringbuffer.c

727

*cs++ = i915_mmio_reg_offset(mbox_reg);

sys/dev/drm/i915/intel_uncore.c

1093

i915_mmio_reg_offset(reg)))

sys/dev/drm/i915/intel_uncore.c

1151

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/drm/i915/intel_uncore.c

1263

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/drm/i915/intel_uncore.c

1680

u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);

sys/dev/drm/i915/intel_uncore.c

2314

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/drm/i915/intel_uncore.c

2337

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/drm/i915/intel_uncore.c

938

u32 offset = i915_mmio_reg_offset(*reg);

sys/dev/drm/i915/intel_uncore.h

215

readl(base + i915_mmio_reg_offset(reg))

sys/dev/drm/i915/intel_uncore.h

217

writel(value, base + i915_mmio_reg_offset(reg))

sys/dev/drm/i915/intel_workarounds.c

1071

w->nopid = i915_mmio_reg_offset(RING_NOPID(engine->mmio_base));

sys/dev/drm/i915/intel_workarounds.c

1113

i915_mmio_reg_offset(w->reg[i]));

sys/dev/drm/i915/intel_workarounds.c

70

unsigned int addr = i915_mmio_reg_offset(reg);