sys/dev/drm/i915/i915_drv.h

3883

return i915_ggtt_offset(i915->gt.scratch);

sys/dev/drm/i915/i915_gem.c

1219

node.start = i915_ggtt_offset(vma);

sys/dev/drm/i915/i915_gem.c

1422

node.start = i915_ggtt_offset(vma);

sys/dev/drm/i915/i915_gem.c

4876

i915_ggtt_offset(vma), alignment,

sys/dev/drm/i915/i915_gem_gtt.c

2043

u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE;

sys/dev/drm/i915/i915_gem_render_state.c

119

so->batch_offset = i915_ggtt_offset(so->vma);

sys/dev/drm/i915/i915_gpu_error.c

1313

erq->start = i915_ggtt_offset(request->ring->vma);

sys/dev/drm/i915/i915_perf.c

1257

i915->perf.oa.specific_ctx_id = i915_ggtt_offset(ce->state);

sys/dev/drm/i915/i915_perf.c

1386

u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);

sys/dev/drm/i915/i915_perf.c

1435

u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);

sys/dev/drm/i915/i915_perf.c

1537

i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma),

sys/dev/drm/i915/i915_perf.c

522

u32 gtt_offset = i915_ggtt_offset(vma);

sys/dev/drm/i915/i915_perf.c

657

u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);

sys/dev/drm/i915/i915_perf.c

946

u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);

sys/dev/drm/i915/intel_drv.h

1671

return i915_ggtt_offset(state->vma);

sys/dev/drm/i915/intel_engine_cs.c

1390

i915_ggtt_offset(rq->ring->vma));

sys/dev/drm/i915/intel_engine_cs.c

1494

i915_ggtt_offset(rq->ring->vma));

sys/dev/drm/i915/intel_engine_cs.c

555

engine->status_page.ggtt_offset = i915_ggtt_offset(vma);

sys/dev/drm/i915/intel_fbc.c

254

i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);

sys/dev/drm/i915/intel_fbdev.c

266

info->fix.smem_start = dev->mode_config.fb_base + i915_ggtt_offset(vma);

sys/dev/drm/i915/intel_fbdev.c

299

fb->width, fb->height, i915_ggtt_offset(vma));

sys/dev/drm/i915/intel_guc.h

140

u32 offset = i915_ggtt_offset(vma);

sys/dev/drm/i915/intel_lrc.c

1375

i915_ggtt_offset(ce->ring->vma);

sys/dev/drm/i915/intel_lrc.c

1993

regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);

sys/dev/drm/i915/intel_lrc.c

233

desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;

sys/dev/drm/i915/intel_lrc.c

2702

u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);

sys/dev/drm/i915/intel_lrc.c

2714

u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);

sys/dev/drm/i915/intel_overlay.c

1326

overlay->flip_addr = i915_ggtt_offset(vma);

sys/dev/drm/i915/intel_overlay.c

806

iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);

sys/dev/drm/i915/intel_overlay.c

823

iowrite32(i915_ggtt_offset(vma) + params->offset_U,

sys/dev/drm/i915/intel_overlay.c

825

iowrite32(i915_ggtt_offset(vma) + params->offset_V,

sys/dev/drm/i915/intel_ringbuffer.c

1625

*cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,

sys/dev/drm/i915/intel_ringbuffer.c

1633

*cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;

sys/dev/drm/i915/intel_ringbuffer.c

543

I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));

sys/dev/drm/i915/intel_ringbuffer.c

573

i915_ggtt_offset(ring->vma));