sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

100

regval = REG_READ(AFMT_VBI_PACKET_CONTROL);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

101

REG_UPDATE(AFMT_VBI_PACKET_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

134

REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

89

REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

96

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

119

SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

120

SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

121

SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

60

SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

645

uint32_t AFMT_VBI_PACKET_CONTROL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

79

REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

86

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

89

regval = REG_READ(AFMT_VBI_PACKET_CONTROL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

90

REG_UPDATE(AFMT_VBI_PACKET_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

112

uint32_t AFMT_VBI_PACKET_CONTROL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

46

SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \