sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

517

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1335

pipe_ctx->plane_res.hubp = pool->hubps[i];

sys/dev/drm/amd/display/dc/core/dc_resource.c

1724

pipe_ctx->plane_res.hubp = pool->hubps[i];

sys/dev/drm/amd/display/dc/core/dc_stream.c

252

(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

102

static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

104

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1052

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1055

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1060

hubp->curs_attr = *attr;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1084

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1088

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

110

static void hubp1_vready_workaround(struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1103

if (hubp->curs_attr.address.quad_part == 0)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1131

if (src_x_offset + (int)hubp->curs_attr.width <= 0)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1137

if (src_y_offset + (int)hubp->curs_attr.height <= 0)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

114

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1141

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1159

void hubp1_clk_cntl(struct hubp *hubp, bool enable)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1161

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1167

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1169

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

134

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

138

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

156

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

161

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

196

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

200

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

229

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

232

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

310

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

314

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

41

void hubp1_set_blank(struct hubp *hubp, bool blank)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

43

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

476

hubp->request_address = *address;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

481

void hubp1_dcc_control(struct hubp *hubp, bool enable,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

486

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

496

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

505

hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

506

hubp1_program_tiling(hubp, tiling_info, format);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

507

hubp1_program_size(hubp, format, plane_size, dcc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

508

hubp1_program_rotation(hubp, rotation, horizontal_mirror);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

509

hubp1_program_pixel_format(hubp, format);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

513

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

516

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

547

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

551

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

65

hubp->mpcc_id = 0xf;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

66

hubp->opp_id = 0xf;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

679

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

688

hubp1_program_requestor(hubp, rq_regs);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

689

hubp1_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

690

hubp1_vready_workaround(hubp, pipe_dest);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

693

bool hubp1_is_flip_pending(struct hubp *hubp)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

696

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

70

static void hubp1_disconnect(struct hubp *hubp)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

711

if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

72

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

720

static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

723

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

749

static void hubp1_set_vm_context0_settings(struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

752

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

785

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

789

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

81

static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

818

void hubp1_read_state(struct hubp *hubp)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

820

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

83

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

90

static unsigned int hubp1_get_underflow_status(struct hubp *hubp)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

93

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

30

#define TO_DCN10_HUBP(hubp)\

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

31

container_of(hubp, struct dcn10_hubp, base)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

658

struct hubp base;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

666

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

676

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

681

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

685

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

689

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

695

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

700

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

704

void hubp1_dcc_control(struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

709

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

713

bool hubp1_is_flip_pending(struct hubp *hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

716

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

720

struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

724

void hubp1_set_blank(struct hubp *hubp, bool blank);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

726

void min_set_viewport(struct hubp *hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

730

void hubp1_clk_cntl(struct hubp *hubp, bool enable);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

731

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h

741

void hubp1_read_state(struct hubp *hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1060

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1066

pipe_ctx->plane_res.hubp = hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1069

hubp->mpcc_id = dpp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1070

hubp->opp_id = 0xf;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1071

hubp->power_gated = false;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1095

pipe_ctx->plane_res.hubp = NULL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1204

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1205

pipe_ctx->plane_res.hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

130

struct hubp *hubp = pool->hubps[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

131

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

133

hubp->funcs->hubp_read_state(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

138

hubp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1610

static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1612

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1619

hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1620

hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1637

pipe_ctx->plane_res.hubp->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1640

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1685

dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1943

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1996

mpcc_id = hubp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2020

hubp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2025

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2026

hubp->mpcc_id = mpcc_id;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2048

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2077

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2079

hubp->funcs->hubp_setup(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2080

hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2109

hubp->funcs->mem_program_viewport(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2110

hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2128

hubp->opp_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2139

hubp->funcs->hubp_program_surface_config(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2140

hubp,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2150

hubp->power_gated = false;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2155

hubp->funcs->set_blank(hubp, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2376

old_pipe_ctx->plane_res.hubp &&

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2377

old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2556

static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2584

struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2588

hubp->funcs->set_blank(hubp, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2619

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2620

pipe_ctx->plane_res.hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2637

struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2639

if (hubp->funcs->hubp_update_dchub)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2640

hubp->funcs->hubp_update_dchub(hubp, dh_data);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2649

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2668

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2669

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2676

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2677

pipe_ctx->plane_res.hubp, attributes);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

542

struct hubp *hubp = dc->res_pool->hubps[0];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

547

hubp->funcs->set_blank(hubp, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

562

struct hubp *hubp = dc->res_pool->hubps[0];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

585

hubp->funcs->set_hubp_blank_en(hubp, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

780

struct hubp *hubp ;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

791

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

792

if (hubp != NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

793

if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

816

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

818

if (hubp != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

819

hubp->funcs->set_hubp_blank_en(hubp, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

829

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

831

if (hubp != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

832

hubp->funcs->hubp_disable_control(hubp, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

839

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

841

if (hubp != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

842

hubp->funcs->hubp_disable_control(hubp, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

851

hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

853

if (hubp != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

854

hubp->funcs->set_hubp_blank_en(hubp, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

882

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

902

if (hubp->funcs->hubp_disconnect)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

903

hubp->funcs->hubp_disconnect(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

919

hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

933

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

935

int opp_id = hubp->opp_id;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

939

hubp->funcs->hubp_clk_cntl(hubp, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

948

hubp->power_gated = true;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

965

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

133

struct hubp *hubp = pool->hubps[i];

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

134

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

136

hubp->funcs->hubp_read_state(hubp);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

143

hubp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

162

hubp->inst,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1104

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

963

static struct hubp *dcn10_hubp_create(

sys/dev/drm/amd/display/dc/inc/core_types.h

138

struct hubp *hubps[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

205

struct hubp *hubp;

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

102

bool (*hubp_is_flip_pending)(struct hubp *hubp);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

104

void (*hubp_update_dchub)(struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

107

void (*set_blank)(struct hubp *hubp, bool blank);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

108

void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

111

struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

115

struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

119

void (*hubp_disconnect)(struct hubp *hubp);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

121

void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

122

void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

123

void (*hubp_read_state)(struct hubp *hubp);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

124

void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

125

unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

60

struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

66

void (*dcc_control)(struct hubp *hubp, bool enable,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

69

struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

74

struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

79

struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

85

struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

89

struct hubp *hubp,

sys/dev/drm/amd/display/dc/inc/hw/hubp.h

93

struct hubp *hubp,