sys/dev/drm/amd/amdgpu/dce_v10_0.c

1208

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1234

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1335

REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

171

SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

63

SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

649

uint32_t AFMT_AUDIO_SRC_CONTROL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1174

REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

116

uint32_t AFMT_AUDIO_SRC_CONTROL;

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

50

SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \

sys/dev/drm/radeon/dce6_afmt.c

128

WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,