sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

113

config->gb_addr_config = adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

156

config->gb_addr_config = adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

506

config[no_regs++] = adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

170

unsigned gb_addr_config;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

178

struct gb_addr_config gb_addr_config_fields;

sys/dev/drm/amd/amdgpu/cik.c

1061

return adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/cik_sdma.c

452

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1904

WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1905

WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1906

WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4329

u32 gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4350

gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4367

gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4384

gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4403

gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4451

gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4455

gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4458

gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4461

gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4464

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1782

u32 gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1804

gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1821

gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1836

gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1851

gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1868

gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1885

gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1902

gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1919

gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1970

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1973

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1976

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1979

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3836

WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3837

WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3838

WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1389

u32 gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1401

gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1409

gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1418

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1419

gb_addr_config &= ~0xf3e777ff;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1420

gb_addr_config |= 0x22014042;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1433

gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1435

gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1442

adev->gfx.config.gb_addr_config = gb_addr_config;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1446

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1455

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1460

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1465

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1470

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1475

adev->gfx.config.gb_addr_config,

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

427

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

665

adev->gfx.config.gb_addr_config & 0x70);

sys/dev/drm/amd/amdgpu/soc15.c

324

return adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

580

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

581

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

582

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

282

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

283

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

284

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

614

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

615

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

616

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

707

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

709

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

711

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1055

tmp = adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

324

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

326

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

328

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

330

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

332

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

334

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

336

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

338

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

340

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

342

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

344

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

346

adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

400

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

402

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

404

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

406

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

408

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

410

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

412

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

414

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

416

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

418

adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vi.c

585

return adev->gfx.config.gb_addr_config;

sys/dev/drm/amd/include/kgd_kfd_interface.h

178

uint32_t gb_addr_config;

sys/dev/drm/radeon/cik.c

3196

u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);

sys/dev/drm/radeon/cik.c

3218

gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/cik.c

3235

gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/cik.c

3252

gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/cik.c

3271

gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/cik.c

3305

gb_addr_config &= ~ROW_SIZE_MASK;

sys/dev/drm/radeon/cik.c

3309

gb_addr_config |= ROW_SIZE(0);

sys/dev/drm/radeon/cik.c

3312

gb_addr_config |= ROW_SIZE(1);

sys/dev/drm/radeon/cik.c

3315

gb_addr_config |= ROW_SIZE(2);

sys/dev/drm/radeon/cik.c

3346

((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;

sys/dev/drm/radeon/cik.c

3348

((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;

sys/dev/drm/radeon/cik.c

3350

WREG32(GB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3351

WREG32(HDP_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3352

WREG32(DMIF_ADDR_CALC, gb_addr_config);

sys/dev/drm/radeon/cik.c

3353

WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);

sys/dev/drm/radeon/cik.c

3354

WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);

sys/dev/drm/radeon/cik.c

3355

WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3356

WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3357

WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3117

u32 gb_addr_config;

sys/dev/drm/radeon/evergreen.c

3158

gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3180

gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3202

gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3225

gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3247

gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3275

gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3297

gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3319

gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3341

gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3363

gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/evergreen.c

3432

((gb_addr_config & 0x30000000) >> 28) << 12;

sys/dev/drm/radeon/evergreen.c

3480

WREG32(GB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3481

WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3482

WREG32(HDP_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3483

WREG32(DMA_TILING_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3484

WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3485

WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3486

WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3498

tmp = gb_addr_config & NUM_PIPES_MASK;

sys/dev/drm/radeon/ni.c

1010

gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/ni.c

1041

tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;

sys/dev/drm/radeon/ni.c

1043

tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;

sys/dev/drm/radeon/ni.c

1045

tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;

sys/dev/drm/radeon/ni.c

1047

tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;

sys/dev/drm/radeon/ni.c

1049

tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;

sys/dev/drm/radeon/ni.c

1051

tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;

sys/dev/drm/radeon/ni.c

1097

((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;

sys/dev/drm/radeon/ni.c

1099

((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;

sys/dev/drm/radeon/ni.c

1137

WREG32(GB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1138

WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1140

WREG32(DMIF_ADDR_CALC, gb_addr_config);

sys/dev/drm/radeon/ni.c

1141

WREG32(HDP_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1142

WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/ni.c

1143

WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/ni.c

1144

WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1145

WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1146

WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1158

tmp = gb_addr_config & NUM_PIPES_MASK;

sys/dev/drm/radeon/ni.c

903

u32 gb_addr_config = 0;

sys/dev/drm/radeon/ni.c

936

gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/si.c

3081

u32 gb_addr_config = 0;

sys/dev/drm/radeon/si.c

3104

gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/si.c

3121

gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/si.c

3139

gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/si.c

3156

gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/si.c

3173

gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;

sys/dev/drm/radeon/si.c

3209

gb_addr_config &= ~ROW_SIZE_MASK;

sys/dev/drm/radeon/si.c

3213

gb_addr_config |= ROW_SIZE(0);

sys/dev/drm/radeon/si.c

3216

gb_addr_config |= ROW_SIZE(1);

sys/dev/drm/radeon/si.c

3219

gb_addr_config |= ROW_SIZE(2);

sys/dev/drm/radeon/si.c

3260

((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;

sys/dev/drm/radeon/si.c

3262

((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;

sys/dev/drm/radeon/si.c

3264

WREG32(GB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3265

WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3266

WREG32(DMIF_ADDR_CALC, gb_addr_config);

sys/dev/drm/radeon/si.c

3267

WREG32(HDP_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3268

WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/si.c

3269

WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/si.c

3271

WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3272

WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3273

WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);