fw_info
struct drm_amdgpu_info_firmware fw_info;
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
i, fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
fw_info.feature, fw_info.ver);
static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
fw_info->ver = adev->vce.fw_version;
fw_info->feature = adev->vce.fb_version;
fw_info->ver = adev->uvd.fw_version;
fw_info->feature = 0;
fw_info->ver = adev->vcn.fw_version;
fw_info->feature = 0;
fw_info->ver = adev->gmc.fw_version;
fw_info->feature = 0;
fw_info->ver = adev->gfx.me_fw_version;
fw_info->feature = adev->gfx.me_feature_version;
fw_info->ver = adev->gfx.pfp_fw_version;
fw_info->feature = adev->gfx.pfp_feature_version;
fw_info->ver = adev->gfx.ce_fw_version;
fw_info->feature = adev->gfx.ce_feature_version;
fw_info->ver = adev->gfx.rlc_fw_version;
fw_info->feature = adev->gfx.rlc_feature_version;
fw_info->ver = adev->gfx.rlc_srlc_fw_version;
fw_info->feature = adev->gfx.rlc_srlc_feature_version;
fw_info->ver = adev->gfx.rlc_srlg_fw_version;
fw_info->feature = adev->gfx.rlc_srlg_feature_version;
fw_info->ver = adev->gfx.rlc_srls_fw_version;
fw_info->feature = adev->gfx.rlc_srls_feature_version;
fw_info->ver = adev->gfx.mec_fw_version;
fw_info->feature = adev->gfx.mec_feature_version;
fw_info->ver = adev->gfx.mec2_fw_version;
fw_info->feature = adev->gfx.mec2_feature_version;
fw_info->ver = adev->pm.fw_version;
fw_info->feature = 0;
fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
fw_info->ver = adev->psp.sos_fw_version;
fw_info->feature = adev->psp.sos_feature_version;
fw_info->ver = adev->psp.asd_fw_version;
fw_info->feature = adev->psp.asd_feature_version;
fw_info->ver = adev->dm.dmcu_fw_version;
fw_info->feature = 0;
struct drm_amdgpu_info_firmware fw_info;
ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
return copy_to_user(out, &fw_info,
min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
struct dc_firmware_info fw_info = { { 0 } };
dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
struct dc_firmware_info fw_info = { { 0 } };
&fw_info) != BP_RESULT_OK)
calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
fw_info.pll_info.min_output_pxl_clk_pll_frequency;
fw_info.pll_info.max_output_pxl_clk_pll_frequency;
fw_info.pll_info.max_input_pxl_clk_pll_frequency;
fw_info.pll_info.min_input_pxl_clk_pll_frequency;
struct dc_firmware_info fw_info = { { 0 } };
clk_src->bios, &fw_info) != BP_RESULT_OK) {
fw_info.external_clock_source_frequency_for_dp;
clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
struct dc_firmware_info fw_info = { { 0 } };
clk_src->bios, &fw_info) != BP_RESULT_OK) {
clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp;
struct dc_firmware_info fw_info = { { 0 } };
bp->funcs->get_firmware_info(bp, &fw_info);
fw_info.smu_gpu_pll_output_freq;
struct dc_firmware_info fw_info = { { 0 } };
bp->funcs->get_firmware_info(bp, &fw_info);
clk_dce->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
ATOM_COMMON_TABLE_HEADER *fw_info;
fw_info = (ATOM_COMMON_TABLE_HEADER *)
if (fw_info == NULL)
if ((fw_info->ucTableFormatRevision == 2) &&
(le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V2_1))) {
(ATOM_FIRMWARE_INFO_V2_1 *)fw_info;
(ATOM_FIRMWARE_INFO *)fw_info;
ATOM_FIRMWARE_INFO *fw_info;
fw_info = (ATOM_FIRMWARE_INFO *)
if (fw_info == NULL)
clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock));
struct atom_firmware_info_v3_2 *fw_info)
boot_values->ulRevision = fw_info->firmware_revision;
boot_values->ulGfxClk = fw_info->bootup_sclk_in10khz;
boot_values->ulUClk = fw_info->bootup_mclk_in10khz;
boot_values->usVddc = fw_info->bootup_vddc_mv;
boot_values->usVddci = fw_info->bootup_vddci_mv;
boot_values->usMvddc = fw_info->bootup_mvddc_mv;
boot_values->usVddGfx = fw_info->bootup_vddgfx_mv;
boot_values->ucCoolingID = fw_info->coolingsolution_id;
struct atom_firmware_info_v3_1 *fw_info)
boot_values->ulRevision = fw_info->firmware_revision;
boot_values->ulGfxClk = fw_info->bootup_sclk_in10khz;
boot_values->ulUClk = fw_info->bootup_mclk_in10khz;
boot_values->usVddc = fw_info->bootup_vddc_mv;
boot_values->usVddci = fw_info->bootup_vddci_mv;
boot_values->usMvddc = fw_info->bootup_mvddc_mv;
boot_values->usVddGfx = fw_info->bootup_vddgfx_mv;
boot_values->ucCoolingID = fw_info->coolingsolution_id;
le32_to_cpu(fw_info->ul3DAccelerationEngineClock) & 0x7FF;
le16_to_cpu(fw_info->usBootUpVDDCVoltage);
le16_to_cpu(fw_info->usBootUpVDDCVoltage);
const ATOM_FIRMWARE_INFO_V2_1 *fw_info)
const ATOM_COMMON_TABLE_HEADER *fw_info = NULL;
fw_info = smu_atom_get_data_table(hwmgr->adev,
if ((fw_info->ucTableFormatRevision == 1)
&& (le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V1_4)))
(const ATOM_FIRMWARE_INFO_V1_4 *)fw_info);
else if ((fw_info->ucTableFormatRevision == 2)
&& (le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V2_1)))
(const ATOM_FIRMWARE_INFO_V2_1 *)fw_info);
const ATOM_FIRMWARE_INFO_V1_4 *fw_info)
le32_to_cpu(fw_info->ulASICMaxEngineClock);
le32_to_cpu(fw_info->ulASICMaxMemoryClock);
ATOM_FIRMWARE_INFO_V2_2 *fw_info;
fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
if (!fw_info)
le32_to_cpu(fw_info->ulDefaultEngineClock);
le32_to_cpu(fw_info->ulDefaultMemoryClock);
le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
le16_to_cpu(fw_info->usBootUpVDDCVoltage);
le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
struct intel_fw_info fw_info[20];
if (package_header->fw_info[i].substepping == '*' &&
si->stepping == package_header->fw_info[i].stepping) {
dmc_offset = package_header->fw_info[i].offset;
} else if (si->stepping == package_header->fw_info[i].stepping &&
si->substepping == package_header->fw_info[i].substepping) {
dmc_offset = package_header->fw_info[i].offset;
} else if (package_header->fw_info[i].stepping == '*' &&
package_header->fw_info[i].substepping == '*')
dmc_offset = package_header->fw_info[i].offset;
struct fw_info *fw)
struct fw_info fw;
struct fw_info fw;
struct fw_info fw;
struct fw_info fw;
struct fw_info fw;
struct fw_info *);