for_each_if
for_each_if(vgpu->active)
for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
for_each_if((__crtc)->plane_ids_mask & BIT(__p))
for_each_if((__mask) & BIT(__p))
for_each_if ((__mask) & (1 << (__t)))
for_each_if((__ports_mask) & BIT(__port))
for_each_if((plane_mask) & \
for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
for_each_if(intel_encoder_is_dp(intel_encoder))
for_each_if((intel_encoder)->base.crtc == (__crtc))
for_each_if((intel_connector)->base.encoder == (__encoder))
for_each_if(BIT_ULL(domain) & (mask))
for_each_if((__power_well)->desc->domains & (__domain_mask))
for_each_if((__power_well)->desc->domains & (__domain_mask))
for_each_if(plane)
for_each_if(crtc)
for_each_if(plane)
for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
for_each_if ((__state)->connectors[__i].ptr && \
for_each_if ((__state)->connectors[__i].ptr && \
for_each_if ((__state)->connectors[__i].ptr && \
for_each_if ((__state)->crtcs[__i].ptr && \
for_each_if ((__state)->crtcs[__i].ptr && \
for_each_if ((__state)->crtcs[__i].ptr && \
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((plane_state = \
for_each_if((encoder) = \
for_each_if ((encoder_mask) & drm_encoder_mask(encoder))
for_each_if ((plane_mask) & drm_plane_mask(plane))
for_each_if (plane->type == DRM_PLANE_TYPE_OVERLAY)