drm_dp_dpcd_readb
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
ret = drm_dp_dpcd_readb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);
ret = drm_dp_dpcd_readb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
if (drm_dp_dpcd_readb(&intel_dp->aux,
if (drm_dp_dpcd_readb(&intel_dp->aux,
if (drm_dp_dpcd_readb(&intel_dp->aux,
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
if (drm_dp_dpcd_readb(&intel_dp->aux,
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)