crypto/openssh/sshbuf.c
372
sshbuf_reserve(struct sshbuf *buf, size_t len, u_char **dpp)
crypto/openssh/sshbuf.c
377
if (dpp != NULL)
crypto/openssh/sshbuf.c
378
*dpp = NULL;
crypto/openssh/sshbuf.c
386
if (dpp != NULL)
crypto/openssh/sshbuf.c
387
*dpp = dp;
crypto/openssh/sshbuf.h
130
int sshbuf_reserve(struct sshbuf *buf, size_t len, u_char **dpp);
lib/libc/resolv/res_mkquery.c
106
u_char *dnptrs[20], **dpp, **lastdnptr;
lib/libc/resolv/res_mkquery.c
128
dpp = dnptrs;
lib/libc/resolv/res_mkquery.c
129
*dpp++ = buf;
lib/libc/resolv/res_mkquery.c
130
*dpp++ = NULL;
lib/libc/resolv/res_mkupdate.c
100
u_char *dnptrs[20], **dpp, **lastdnptr;
lib/libc/resolv/res_mkupdate.c
118
dpp = dnptrs;
lib/libc/resolv/res_mkupdate.c
119
*dpp++ = buf;
lib/libc/resolv/res_mkupdate.c
120
*dpp++ = NULL;
sbin/mountd/mountd.c
1516
add_expdir(struct dirlist **dpp, char *cp, int len)
sbin/mountd/mountd.c
1523
dp->dp_left = *dpp;
sbin/mountd/mountd.c
1530
*dpp = dp;
sbin/mountd/mountd.c
1577
add_dlist(struct dirlist **dpp, struct dirlist *newdp, struct grouplist *grp,
sbin/mountd/mountd.c
1584
dp = *dpp;
sbin/mountd/mountd.c
1598
*dpp = dp;
sys/bus/u4b/usb_generic.c
1825
ugen_get_port_path(struct usb_fifo *f, struct usb_device_port_path *dpp)
sys/bus/u4b/usb_generic.c
1834
dpp->udp_bus = device_get_unit(udev->bus->bdev);
sys/bus/u4b/usb_generic.c
1835
dpp->udp_index = udev->device_index;
sys/bus/u4b/usb_generic.c
1849
dpp->udp_port_level = nlevel;
sys/bus/u4b/usb_generic.c
1854
dpp->udp_port_no[--nlevel] = next->port_no;
sys/bus/u4b/usb_generic.c
2064
struct usb_device_port_path *dpp;
sys/bus/u4b/usb_generic.c
2237
error = ugen_get_port_path(f, u.dpp);
sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c
260
if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c
275
input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c
520
secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
sys/dev/drm/amd/display/dc/core/dc_resource.c
1150
if (pipe_ctx->plane_res.dpp != NULL)
sys/dev/drm/amd/display/dc/core/dc_resource.c
1151
res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
sys/dev/drm/amd/display/dc/core/dc_resource.c
1152
pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
sys/dev/drm/amd/display/dc/core/dc_resource.c
1163
if (pipe_ctx->plane_res.dpp != NULL)
sys/dev/drm/amd/display/dc/core/dc_resource.c
1164
res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
sys/dev/drm/amd/display/dc/core/dc_resource.c
1165
pipe_ctx->plane_res.dpp,
sys/dev/drm/amd/display/dc/core/dc_resource.c
1337
pipe_ctx->plane_res.dpp = pool->dpps[i];
sys/dev/drm/amd/display/dc/core/dc_resource.c
1727
pipe_ctx->plane_res.dpp = pool->dpps[i];
sys/dev/drm/amd/display/dc/core/dc_stream.c
254
(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
sys/dev/drm/amd/display/dc/dce/dce_clocks.c
556
pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
sys/dev/drm/amd/display/dc/dce/dce_clocks.c
557
pipe_ctx->plane_res.dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
101
void dpp_read_state(struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
104
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
131
void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
142
struct dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
155
dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
161
dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
162
scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
198
if (!dpp->ctx->dc->debug.always_scale) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
212
void dpp_reset(struct dpp *dpp_base)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
214
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
216
dpp->filter_h_c = NULL;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
217
dpp->filter_v_c = NULL;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
218
dpp->filter_h = NULL;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
219
dpp->filter_v = NULL;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
221
memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
222
memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
228
struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
230
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
244
re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
245
if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
249
dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
251
if (dpp->is_write_to_ram_a_safe)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
258
dpp->pwl_data = *params;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
260
re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
261
dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
283
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
286
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
298
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
310
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
42
dpp->tf_regs->reg
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
428
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
431
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
448
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
45
dpp->base.ctx
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
454
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
477
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
480
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
489
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
49
dpp->tf_shift->field_name, dpp->tf_mask->field_name
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
493
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
496
if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
543
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
550
dpp->base.ctx = ctx;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
552
dpp->base.inst = inst;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
553
dpp->base.funcs = &dcn10_dpp_funcs;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
554
dpp->base.caps = &dcn10_dpp_cap;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
556
dpp->tf_regs = tf_regs;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
557
dpp->tf_shift = tf_shift;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
558
dpp->tf_mask = tf_mask;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
560
dpp->lb_pixel_depth_supported =
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
565
dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c
566
dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1345
struct dpp base;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1370
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1374
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1381
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1396
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1400
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1404
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1408
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1414
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1418
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1424
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1428
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1431
void dpp1_full_bypass(struct dpp *dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1434
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1437
void dpp1_set_degamma_pwl(struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1441
void dpp_read_state(struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1444
void dpp_reset(struct dpp *dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1447
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1452
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1456
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1461
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1466
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1469
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1473
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1477
struct dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1481
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1485
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1492
void dpp1_full_bypass(struct dpp *dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1496
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
1501
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
30
#define TO_DCN10_DPP(dpp)\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
31
container_of(dpp, struct dcn10_dpp, base)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
123
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
149
gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
150
gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
151
gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
152
gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
160
dpp->base.ctx,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
170
dpp->base.ctx,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
180
dpp->base.ctx,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
192
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
195
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
200
program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
211
program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
216
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
244
gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
245
gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
246
gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
247
gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
262
dpp->base.ctx,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
271
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
274
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
284
dpp1_cm_program_color_matrix(dpp, regval);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
288
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
291
reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
292
reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
293
reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
294
reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
295
reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
296
reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
297
reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
298
reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
300
reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
301
reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
302
reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
303
reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
304
reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
305
reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
306
reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
307
reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
308
reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
309
reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
310
reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
311
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
315
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
318
reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
319
reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
320
reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
321
reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
322
reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
323
reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
324
reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
325
reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
327
reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
328
reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
329
reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
330
reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
331
reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
332
reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
333
reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
334
reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
335
reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
336
reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
337
reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
338
reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
341
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
344
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
346
dpp1_cm_program_color_matrix(dpp, regval);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
349
void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
352
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
359
void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
364
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
380
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
383
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
394
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
397
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
400
dpp1_cm_get_reg_field(dpp, &gam_regs);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
417
cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
423
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
426
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
429
dpp1_cm_get_reg_field(dpp, &gam_regs);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
43
dpp->tf_regs->reg
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
446
cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
450
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
455
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
46
dpp->base.ctx
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
498
gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
499
gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
50
dpp->tf_shift->field_name, dpp->tf_mask->field_name
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
500
gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
501
gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
516
dpp->base.ctx,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
526
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
529
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
547
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
550
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
553
dpp1_cm_get_degamma_reg_field(dpp, &gam_regs);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
571
cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
576
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
579
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
582
dpp1_cm_get_degamma_reg_field(dpp, &gam_regs);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
599
cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
603
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
606
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
614
struct dpp *dpp_base)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
616
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
623
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
626
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
647
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
650
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
660
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
665
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
681
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
688
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
710
void dpp1_set_degamma_pwl(struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
728
void dpp1_full_bypass(struct dpp *dpp_base)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
730
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
743
if (dpp->tf_mask->CM_BYPASS_EN)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
750
static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
755
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
782
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
786
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
831
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
834
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
118
struct dcn10_dpp *dpp, const struct scaler_data *data)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
170
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
204
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
209
if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
255
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
293
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
335
filter_updated = (filter_h && (filter_h != dpp->filter_h))
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
336
|| (filter_v && (filter_v != dpp->filter_v));
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
343
filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
344
|| (filter_v_c && (filter_v_c != dpp->filter_v_c));
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
352
dpp, scl_data->taps.h_taps,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
355
dpp->filter_h = filter_h;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
358
dpp, scl_data->taps.v_taps,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
361
dpp->filter_v = filter_v;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
365
dpp, scl_data->taps.h_taps_c,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
370
dpp, scl_data->taps.v_taps_c,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
374
dpp->filter_h_c = filter_h_c;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
375
dpp->filter_v_c = filter_v_c;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
378
scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
379
dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
43
dpp->tf_regs->reg
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
46
dpp->base.ctx
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
463
static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
473
if (dpp->base.ctx->dc->debug.use_max_lb)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
476
dpp->base.caps->dscl_calc_lb_num_partitions(
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
483
dpp->base.caps->dscl_calc_lb_num_partitions(
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
492
dpp->base.caps->dscl_calc_lb_num_partitions(
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
50
dpp->tf_shift->field_name, dpp->tf_mask->field_name
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
500
dpp->base.caps->dscl_calc_lb_num_partitions(
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
512
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
516
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
522
dpp1_dscl_set_overscan(dpp, scl_data);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
524
dpp1_dscl_set_otg_blank(dpp, scl_data);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
531
lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
532
dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
560
dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
566
struct dcn10_dpp *dpp, const struct scaler_data *data)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
626
struct dcn10_dpp *dpp, const struct rect *recout)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
629
if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
643
- visual_confirm_on * 4 * (dpp->base.inst + 1));
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
648
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
652
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
658
if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
663
dpp->scl_data = *scl_data;
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
672
dpp1_dscl_set_recout(dpp, &scl_data->recout);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
688
lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
689
dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
706
dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
715
dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
90
struct dcn10_dpp *dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1061
struct dpp *dpp = dc->res_pool->dpps[i];
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1067
pipe_ctx->plane_res.dpp = dpp;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1068
pipe_ctx->plane_res.mpcc_inst = dpp->inst;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1069
hubp->mpcc_id = dpp->inst;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1221
struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1276
struct dpp *dpp = pipe_ctx->plane_res.dpp;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1278
if (dpp == NULL)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1281
dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1286
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1293
&dpp->regamma_params, false)) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1294
dpp->funcs->dpp_program_regamma_pwl(
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1295
dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1296
&dpp->regamma_params, OPP_REGAMMA_USER);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1298
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1707
pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1716
if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1717
pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1719
if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1720
pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1730
if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1924
static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1929
dpp->funcs->dpp_setup(dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1937
if (dpp->funcs->dpp_program_bias_and_scale)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1938
dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2039
pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2040
pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2049
struct dpp *dpp = pipe_ctx->plane_res.dpp;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2062
dpp->funcs->dpp_dppclk_control(
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2063
dpp,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2091
update_dpp(dpp, plane_state);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2213
pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2214
pipe_ctx->plane_res.dpp, hw_mult);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
253
struct dpp *dpp = pool->dpps[i];
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
256
dpp->funcs->dpp_read_state(dpp, &s);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
263
dpp->inst,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2650
struct dpp *dpp = pipe_ctx->plane_res.dpp;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2669
dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2678
pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2679
pipe_ctx->plane_res.dpp, attributes->color_format);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2690
if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2705
pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2706
pipe_ctx->plane_res.dpp, &opt_attr);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
883
int dpp_id = pipe_ctx->plane_res.dpp->inst;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
912
struct dpp *dpp = pipe_ctx->plane_res.dpp;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
918
dpp_pg_control(hws, dpp->inst, false);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
920
dpp->funcs->dpp_reset(dpp);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
934
struct dpp *dpp = pipe_ctx->plane_res.dpp;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
941
dpp->funcs->dpp_dppclk_control(dpp, false, false);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
341
struct dpp *dpp = pool->dpps[i];
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
344
dpp->funcs->dpp_read_state(dpp, &s);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
351
dpp->inst, s.igam_input_format,
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
1106
idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
560
static void dcn10_dpp_destroy(struct dpp **dpp)
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
562
kfree(TO_DCN10_DPP(*dpp));
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
563
*dpp = NULL;
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
566
static struct dpp *dcn10_dpp_create(
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
570
struct dcn10_dpp *dpp =
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
573
if (!dpp)
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
576
dpp1_construct(dpp, ctx, inst,
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
578
return &dpp->base;
sys/dev/drm/amd/display/dc/inc/core_types.h
141
struct dpp *dpps[MAX_PIPES];
sys/dev/drm/amd/display/dc/inc/core_types.h
209
struct dpp *dpp;
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
102
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
106
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
110
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
114
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
119
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
123
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
127
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
130
void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
134
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
140
void (*dpp_full_bypass)(struct dpp *dpp_base);
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
143
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
147
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
154
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
157
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
161
struct dpp *dpp_base,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
63
void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
65
void (*dpp_reset)(struct dpp *dpp);
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
67
void (*dpp_set_scaler)(struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
71
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
76
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
81
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
85
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
89
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
93
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/dpp.h
97
struct dpp *dpp,
sys/dev/drm/amd/display/dc/inc/hw/opp.h
200
int dpp[MAX_PIPES];
sys/libiconv/iconv_ucs.c
140
*dpp = (void*)dp;
sys/libiconv/iconv_ucs.c
89
struct iconv_cspair *csp, struct iconv_cspair *cspf, void **dpp)
sys/libiconv/iconv_xlat.c
56
struct iconv_cspair *csp, struct iconv_cspair *cspf, void **dpp)
sys/libiconv/iconv_xlat.c
64
*dpp = (void*)dp;
sys/libiconv/iconv_xlat16.c
61
struct iconv_cspair *csp, struct iconv_cspair *cspf, void **dpp)
sys/libiconv/iconv_xlat16.c
91
*dpp = (void*)dp;
usr.bin/tftp/tftpsubs.c
112
*dpp = (struct tftphdr *)b->buf; /* set caller's ptr */
usr.bin/tftp/tftpsubs.c
168
writeit(FILE *file, struct tftphdr **dpp, int ct, int convert)
usr.bin/tftp/tftpsubs.c
175
*dpp = (struct tftphdr *)bfs[current].buf;
usr.bin/tftp/tftpsubs.c
99
struct tftphdr **dpp,
