sys/dev/drm/i915/i915_drv.h

405

struct dpll;

sys/dev/drm/i915/intel_ddi.c

1708

struct dpll clock;

sys/dev/drm/i915/intel_display.c

1009

struct dpll *best_clock)

sys/dev/drm/i915/intel_display.c

10486

u32 dpll = pipe_config->dpll_hw_state.dpll;

sys/dev/drm/i915/intel_display.c

10488

if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)

sys/dev/drm/i915/intel_display.c

10505

u32 dpll = pipe_config->dpll_hw_state.dpll;

sys/dev/drm/i915/intel_display.c

10507

struct dpll clock;

sys/dev/drm/i915/intel_display.c

10511

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

sys/dev/drm/i915/intel_display.c

10527

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>

sys/dev/drm/i915/intel_display.c

10530

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>

sys/dev/drm/i915/intel_display.c

10533

switch (dpll & DPLL_MODE_MASK) {

sys/dev/drm/i915/intel_display.c

10535

clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?

sys/dev/drm/i915/intel_display.c

10539

clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?

sys/dev/drm/i915/intel_display.c

10544

"mode\n", (int)(dpll & DPLL_MODE_MASK));

sys/dev/drm/i915/intel_display.c

10557

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>

sys/dev/drm/i915/intel_display.c

10565

if (dpll & PLL_P1_DIVIDE_BY_TWO)

sys/dev/drm/i915/intel_display.c

10568

clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>

sys/dev/drm/i915/intel_display.c

10571

if (dpll & PLL_P2_DIVIDE_BY_4)

sys/dev/drm/i915/intel_display.c

11757

PIPE_CONF_CHECK_X(dpll_hw_state.dpll);

sys/dev/drm/i915/intel_display.c

1395

I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);

sys/dev/drm/i915/intel_display.c

1418

if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)

sys/dev/drm/i915/intel_display.c

1449

I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);

sys/dev/drm/i915/intel_display.c

1469

if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)

sys/dev/drm/i915/intel_display.c

1513

u32 dpll = crtc_state->dpll_hw_state.dpll;

sys/dev/drm/i915/intel_display.c

1530

dpll |= DPLL_DVO_2X_MODE;

sys/dev/drm/i915/intel_display.c

1542

I915_WRITE(reg, dpll);

sys/dev/drm/i915/intel_display.c

15482

struct dpll clock = {

sys/dev/drm/i915/intel_display.c

15489

u32 dpll, fp;

sys/dev/drm/i915/intel_display.c

15498

dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |

sys/dev/drm/i915/intel_display.c

15521

I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);

sys/dev/drm/i915/intel_display.c

15522

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

15533

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

15537

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

1557

I915_WRITE(reg, dpll);

sys/dev/drm/i915/intel_display.c

1562

I915_WRITE(reg, dpll);

sys/dev/drm/i915/intel_display.c

550

static int pnv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/drm/i915/intel_display.c

562

static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)

sys/dev/drm/i915/intel_display.c

564

return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);

sys/dev/drm/i915/intel_display.c

567

static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/drm/i915/intel_display.c

579

static int vlv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/drm/i915/intel_display.c

591

int chv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/drm/i915/intel_display.c

612

const struct dpll *clock)

sys/dev/drm/i915/intel_display.c

685

int target, int refclk, struct dpll *match_clock,

sys/dev/drm/i915/intel_display.c

686

struct dpll *best_clock)

sys/dev/drm/i915/intel_display.c

6863

static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)

sys/dev/drm/i915/intel_display.c

6865

return (1 << dpll->n) << 16 | dpll->m2;

sys/dev/drm/i915/intel_display.c

6868

static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)

sys/dev/drm/i915/intel_display.c

6870

return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;

sys/dev/drm/i915/intel_display.c

6875

struct dpll *reduced_clock)

sys/dev/drm/i915/intel_display.c

6881

fp = pnv_dpll_compute_fp(&crtc_state->dpll);

sys/dev/drm/i915/intel_display.c

6885

fp = i9xx_dpll_compute_fp(&crtc_state->dpll);

sys/dev/drm/i915/intel_display.c

689

struct dpll clock;

sys/dev/drm/i915/intel_display.c

7003

pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |

sys/dev/drm/i915/intel_display.c

7006

pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;

sys/dev/drm/i915/intel_display.c

7010

pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |

sys/dev/drm/i915/intel_display.c

7020

pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |

sys/dev/drm/i915/intel_display.c

7023

pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;

sys/dev/drm/i915/intel_display.c

7027

pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;

sys/dev/drm/i915/intel_display.c

7045

pipe_config->dpll_hw_state.dpll &

sys/dev/drm/i915/intel_display.c

7049

if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

sys/dev/drm/i915/intel_display.c

7054

bestn = pipe_config->dpll.n;

sys/dev/drm/i915/intel_display.c

7055

bestm1 = pipe_config->dpll.m1;

sys/dev/drm/i915/intel_display.c

7056

bestm2 = pipe_config->dpll.m2;

sys/dev/drm/i915/intel_display.c

7057

bestp1 = pipe_config->dpll.p1;

sys/dev/drm/i915/intel_display.c

7058

bestp2 = pipe_config->dpll.p2;

sys/dev/drm/i915/intel_display.c

7146

pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);

sys/dev/drm/i915/intel_display.c

7149

if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

sys/dev/drm/i915/intel_display.c

7152

bestn = pipe_config->dpll.n;

sys/dev/drm/i915/intel_display.c

7153

bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;

sys/dev/drm/i915/intel_display.c

7154

bestm1 = pipe_config->dpll.m1;

sys/dev/drm/i915/intel_display.c

7155

bestm2 = pipe_config->dpll.m2 >> 22;

sys/dev/drm/i915/intel_display.c

7156

bestp1 = pipe_config->dpll.p1;

sys/dev/drm/i915/intel_display.c

7157

bestp2 = pipe_config->dpll.p2;

sys/dev/drm/i915/intel_display.c

7158

vco = pipe_config->dpll.vco;

sys/dev/drm/i915/intel_display.c

7248

const struct dpll *dpll)

sys/dev/drm/i915/intel_display.c

7259

pipe_config->dpll = *dpll;

sys/dev/drm/i915/intel_display.c

7294

struct dpll *reduced_clock)

sys/dev/drm/i915/intel_display.c

7297

u32 dpll;

sys/dev/drm/i915/intel_display.c

7298

struct dpll *clock = &crtc_state->dpll;

sys/dev/drm/i915/intel_display.c

7302

dpll = DPLL_VGA_MODE_DIS;

sys/dev/drm/i915/intel_display.c

7305

dpll |= DPLLB_MODE_LVDS;

sys/dev/drm/i915/intel_display.c

7307

dpll |= DPLLB_MODE_DAC_SERIAL;

sys/dev/drm/i915/intel_display.c

7311

dpll |= (crtc_state->pixel_multiplier - 1)

sys/dev/drm/i915/intel_display.c

7317

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/drm/i915/intel_display.c

7320

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/drm/i915/intel_display.c

7324

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;

sys/dev/drm/i915/intel_display.c

7326

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

7328

dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

7332

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

sys/dev/drm/i915/intel_display.c

7335

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

sys/dev/drm/i915/intel_display.c

7338

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

sys/dev/drm/i915/intel_display.c

7341

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

sys/dev/drm/i915/intel_display.c

7345

dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

sys/dev/drm/i915/intel_display.c

7348

dpll |= PLL_REF_INPUT_TVCLKINBC;

sys/dev/drm/i915/intel_display.c

7351

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

sys/dev/drm/i915/intel_display.c

7353

dpll |= PLL_REF_INPUT_DREFCLK;

sys/dev/drm/i915/intel_display.c

7355

dpll |= DPLL_VCO_ENABLE;

sys/dev/drm/i915/intel_display.c

7356

crtc_state->dpll_hw_state.dpll = dpll;

sys/dev/drm/i915/intel_display.c

7367

struct dpll *reduced_clock)

sys/dev/drm/i915/intel_display.c

7371

u32 dpll;

sys/dev/drm/i915/intel_display.c

7372

struct dpll *clock = &crtc_state->dpll;

sys/dev/drm/i915/intel_display.c

7376

dpll = DPLL_VGA_MODE_DIS;

sys/dev/drm/i915/intel_display.c

7379

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

7382

dpll |= PLL_P1_DIVIDE_BY_TWO;

sys/dev/drm/i915/intel_display.c

7384

dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

7386

dpll |= PLL_P2_DIVIDE_BY_4;

sys/dev/drm/i915/intel_display.c

7391

dpll |= DPLL_DVO_2X_MODE;

sys/dev/drm/i915/intel_display.c

7395

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

sys/dev/drm/i915/intel_display.c

7397

dpll |= PLL_REF_INPUT_DREFCLK;

sys/dev/drm/i915/intel_display.c

7399

dpll |= DPLL_VCO_ENABLE;

sys/dev/drm/i915/intel_display.c

7400

crtc_state->dpll_hw_state.dpll = dpll;

sys/dev/drm/i915/intel_display.c

743

int target, int refclk, struct dpll *match_clock,

sys/dev/drm/i915/intel_display.c

744

struct dpll *best_clock)

sys/dev/drm/i915/intel_display.c

747

struct dpll clock;

sys/dev/drm/i915/intel_display.c

7632

refclk, NULL, &crtc_state->dpll)) {

sys/dev/drm/i915/intel_display.c

7675

refclk, NULL, &crtc_state->dpll)) {

sys/dev/drm/i915/intel_display.c

7709

refclk, NULL, &crtc_state->dpll)) {

sys/dev/drm/i915/intel_display.c

7743

refclk, NULL, &crtc_state->dpll)) {

sys/dev/drm/i915/intel_display.c

7764

refclk, NULL, &crtc_state->dpll)) {

sys/dev/drm/i915/intel_display.c

7785

refclk, NULL, &crtc_state->dpll)) {

sys/dev/drm/i915/intel_display.c

7828

struct dpll clock;

sys/dev/drm/i915/intel_display.c

7833

if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

sys/dev/drm/i915/intel_display.c

7939

struct dpll clock;

sys/dev/drm/i915/intel_display.c

7944

if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)

sys/dev/drm/i915/intel_display.c

799

int target, int refclk, struct dpll *match_clock,

sys/dev/drm/i915/intel_display.c

800

struct dpll *best_clock)

sys/dev/drm/i915/intel_display.c

803

struct dpll clock;

sys/dev/drm/i915/intel_display.c

8038

pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8046

pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;

sys/dev/drm/i915/intel_display.c

8052

pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |

sys/dev/drm/i915/intel_display.c

850

const struct dpll *calculated_clock,

sys/dev/drm/i915/intel_display.c

851

const struct dpll *best_clock,

sys/dev/drm/i915/intel_display.c

8621

static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)

sys/dev/drm/i915/intel_display.c

8623

return i9xx_dpll_compute_m(dpll) < factor * dpll->n;

sys/dev/drm/i915/intel_display.c

8628

struct dpll *reduced_clock)

sys/dev/drm/i915/intel_display.c

8633

u32 dpll, fp, fp2;

sys/dev/drm/i915/intel_display.c

8646

fp = i9xx_dpll_compute_fp(&crtc_state->dpll);

sys/dev/drm/i915/intel_display.c

8648

if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))

sys/dev/drm/i915/intel_display.c

8660

dpll = 0;

sys/dev/drm/i915/intel_display.c

8663

dpll |= DPLLB_MODE_LVDS;

sys/dev/drm/i915/intel_display.c

8665

dpll |= DPLLB_MODE_DAC_SERIAL;

sys/dev/drm/i915/intel_display.c

8667

dpll |= (crtc_state->pixel_multiplier - 1)

sys/dev/drm/i915/intel_display.c

8672

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/drm/i915/intel_display.c

8675

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/drm/i915/intel_display.c

8693

dpll |= DPLL_SDVO_HIGH_SPEED;

sys/dev/drm/i915/intel_display.c

8696

dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

8698

dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

8700

switch (crtc_state->dpll.p2) {

sys/dev/drm/i915/intel_display.c

8702

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

sys/dev/drm/i915/intel_display.c

8705

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

sys/dev/drm/i915/intel_display.c

8708

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

sys/dev/drm/i915/intel_display.c

8711

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

sys/dev/drm/i915/intel_display.c

8717

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

sys/dev/drm/i915/intel_display.c

8719

dpll |= PLL_REF_INPUT_DREFCLK;

sys/dev/drm/i915/intel_display.c

8721

dpll |= DPLL_VCO_ENABLE;

sys/dev/drm/i915/intel_display.c

8723

crtc_state->dpll_hw_state.dpll = dpll;

sys/dev/drm/i915/intel_display.c

8767

refclk, NULL, &crtc_state->dpll)) {

sys/dev/drm/i915/intel_display.c

893

int target, int refclk, struct dpll *match_clock,

sys/dev/drm/i915/intel_display.c

894

struct dpll *best_clock)

sys/dev/drm/i915/intel_display.c

898

struct dpll clock;

sys/dev/drm/i915/intel_display.c

9113

tmp = pipe_config->dpll_hw_state.dpll;

sys/dev/drm/i915/intel_display.c

953

int target, int refclk, struct dpll *match_clock,

sys/dev/drm/i915/intel_display.c

954

struct dpll *best_clock)

sys/dev/drm/i915/intel_display.c

959

struct dpll clock;

sys/dev/drm/i915/intel_dp.c

1773

pipe_config->dpll = divisor[i].dpll;

sys/dev/drm/i915/intel_dp.c

57

struct dpll dpll;

sys/dev/drm/i915/intel_dp.c

751

&chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {

sys/dev/drm/i915/intel_dpll_mgr.c

1687

struct dpll best_clock;

sys/dev/drm/i915/intel_dpll_mgr.c

3311

void intel_release_shared_dpll(struct intel_shared_dpll *dpll,

sys/dev/drm/i915/intel_dpll_mgr.c

3318

shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);

sys/dev/drm/i915/intel_dpll_mgr.c

3339

hw_state->dpll,

sys/dev/drm/i915/intel_dpll_mgr.c

353

hw_state->dpll = val;

sys/dev/drm/i915/intel_dpll_mgr.c

392

I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);

sys/dev/drm/i915/intel_dpll_mgr.c

403

I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);

sys/dev/drm/i915/intel_dpll_mgr.c

462

hw_state->dpll,

sys/dev/drm/i915/intel_dpll_mgr.h

141

uint32_t dpll;

sys/dev/drm/i915/intel_dpll_mgr.h

334

void intel_release_shared_dpll(struct intel_shared_dpll *dpll,

sys/dev/drm/i915/intel_drv.h

1616

const struct dpll *dpll);

sys/dev/drm/i915/intel_drv.h

1651

struct dpll *best_clock);

sys/dev/drm/i915/intel_drv.h

1652

int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);

sys/dev/drm/i915/intel_drv.h

820

struct dpll dpll;

sys/dev/drm/i915/intel_dvo.c

441

u32 dpll[I915_MAX_PIPES];

sys/dev/drm/i915/intel_dvo.c

478

dpll[pipe] = I915_READ(DPLL(pipe));

sys/dev/drm/i915/intel_dvo.c

479

I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);

sys/dev/drm/i915/intel_dvo.c

486

I915_WRITE(DPLL(pipe), dpll[pipe]);

sys/dev/drm/i915/intel_sdvo.c

1087

struct dpll *clock = &pipe_config->dpll;