sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1007

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1020

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1094

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, 0);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1097

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1109

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, value);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1110

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1111

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, value);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

271

dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

439

dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

536

dm_write_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

546

dm_write_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

718

dm_write_reg_soc15(tg->ctx,

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

741

dm_write_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

807

dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

968

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0);