sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

590

uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

599

reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

903

uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

179

uint32_t value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

196

uint32_t value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

207

value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

261

dm_read_reg_soc15(tg->ctx,

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

324

uint32_t pol_value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

388

uint32_t value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

431

value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

531

value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

628

value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

643

value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

666

uint32_t v_blank_start_end = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

695

uint32_t value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

737

value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

776

uint32_t value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

90

uint32_t value = dm_read_reg_soc15(

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1175

uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);