BWN_PHY_OFDM
BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x1b), ~0x1000);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x6e), 0xe000, 0x3cf);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x1a), ~0x007f, 0x000f);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x1a), ~0x3f80, 0x2b80);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x88), ~0x00ff, 0x001c);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x88), ~0x3f00, 0x0200);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x96), ~0x00ff, 0x001c);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x89), ~0x00ff, 0x0020);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x89), ~0x3f00, 0x0200);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x82), ~0x00ff, 0x002e);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x96), (uint16_t)~0xff00, 0x1a00);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x81), ~0x00ff, 0x0028);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x81), (uint16_t)~0xff00, 0x2c00);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x1b), ~0x001e, 0x0002);
BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x1b), ~0x001e);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x1f), 0x287a);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x22), 0x287a);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x8e), 0x1c00);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x8b), 0x005e);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x8d), 0x0002);
BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x26), ~0x0003);
BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x26), ~0x1000);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xc9), 0x0080);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x2c), 0x005a);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xc9), 0x0080);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xc2), 0x1816);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xc3), 0x8006);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xcc), 0x00ff,
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x7e), 0x78);
BWN_PHY_SET(mac, BWN_PHY_OFDM(0x3e), 0x4);
BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xc3), 0x7fff);
BWN_PHY_OFDM(0xc1), BWN_PHY_OFDM(0xc2),
BWN_PHY_OFDM(0xc3), BWN_PHY_OFDM(0xc4),
BWN_PHY_OFDM(0xc5), BWN_PHY_OFDM(0xc6),
BWN_PHY_OFDM(0xc7), BWN_PHY_OFDM(0xc8),
BWN_PHY_OFDM(0xcf),
BWN_PHY_SET(mac, BWN_PHY_OFDM(0xd0), 0x2);
BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xd0), 0xfffd);
BWN_PHY_OFDM(0xc1), BWN_PHY_OFDM(0xc2),
BWN_PHY_OFDM(0xc3), BWN_PHY_OFDM(0xc4),
BWN_PHY_OFDM(0xc5), BWN_PHY_OFDM(0xc6),
BWN_PHY_OFDM(0xc7), BWN_PHY_OFDM(0xc8),
BWN_PHY_OFDM(0xcf),
{ BWN_PHY_OFDM(0xf9), 0 },
{ BWN_PHY_OFDM(0xfe), 0xffe0, 0x1f },
{ BWN_PHY_OFDM(0xff), 0xffe0, 0xc },
{ BWN_PHY_OFDM(0x100), 0xff00, 0x19 },
{ BWN_PHY_OFDM(0xff), 0x03ff, 0x3c00 },
{ BWN_PHY_OFDM(0xfe), 0xfc1f, 0x3e0 },
{ BWN_PHY_OFDM(0xff), 0xffe0, 0xc },
{ BWN_PHY_OFDM(0x100), 0x00ff, 0x1900 },
BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x10);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0xff00, 0xf4);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0x00ff, 0xf100);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe4), 0xff00, 0x10);
tg.tg_pad = BWN_PHY_READ(mac, BWN_PHY_OFDM(0xfb)) & 0xff;
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfb), 0x8000,
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xfc), (tg->tg_pga << 8) | tg->tg_gm);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfd), 0x8000,
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe6), 0xffe7,
BWN_PHY_SET(mac, BWN_PHY_OFDM(0xe5), 0x8);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfb), 0xe03f, gain << 6);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfd), 0x80ff, gain << 8);
return BWN_PHY_READ(mac, BWN_PHY_OFDM(0xfb)) & 0x7f;
BWN_PHY_OFDM(0xf2 + st->st_phyoffset),
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf0), 0x5f80);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf1), 0);
BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xe5), 0xfff7);
#define BWN_PHY_VERSION_OFDM BWN_PHY_OFDM(0x00)
#define BWN_PHY_BBANDCFG BWN_PHY_OFDM(0x01)
#define BWN_PHY_PWRDOWN BWN_PHY_OFDM(0x03)
#define BWN_PHY_CRSTHRES1_R1 BWN_PHY_OFDM(0x06)
#define BWN_PHY_CRSGAIN_CTL BWN_PHY_OFDM(0x10)
#define BWN_PHY_MINPWR_LEVEL BWN_PHY_OFDM(0x16)
#define BWN_PHY_OFDMSYNCTHRESH0 BWN_PHY_OFDM(0x17)
#define BWN_PHY_IDLEAFTERPKTRXTO BWN_PHY_OFDM(0x1a)
#define BWN_PHY_LNAHPFCTL BWN_PHY_OFDM(0x1c)
#define BWN_PHY_DCOFFSETTRANSIENT BWN_PHY_OFDM(0x1c) /* for LP */
#define BWN_PHY_PREAMBLECONFIRMTO BWN_PHY_OFDM(0x1e)
#define BWN_PHY_CLIPTHRESH BWN_PHY_OFDM(0x1f)
#define BWN_PHY_LPFGAINCTL BWN_PHY_OFDM(0x20)
#define BWN_PHY_CLIPCTRTHRESH BWN_PHY_OFDM(0x20) /* for LP */
#define BWN_PHY_HIGAINDB BWN_PHY_OFDM(0x23)
#define BWN_PHY_LOWGAINDB BWN_PHY_OFDM(0x24)
#define BWN_PHY_VERYLOWGAINDB BWN_PHY_OFDM(0x25)
#define BWN_PHY_GAINMISMATCH BWN_PHY_OFDM(0x26)
#define BWN_PHY_ADIVRELATED BWN_PHY_OFDM(0x27)
#define BWN_PHY_GAINDIRECTMISMATCH BWN_PHY_OFDM(0x27) /* for LP */
#define BWN_PHY_CRS0 BWN_PHY_OFDM(0x29)
#define BWN_PHY_PWR_THRESH1 BWN_PHY_OFDM(0x29) /* for LP */
#define BWN_PHY_ANTDWELL BWN_PHY_OFDM(0x2b)
#define BWN_PHY_DSSS_CONFIRM_CNT BWN_PHY_OFDM(0x2f) /* DSSS Confirm Cnt */
#define BWN_PHY_PEAK_COUNT BWN_PHY_OFDM(0x30)
#define BWN_PHY_GAIN_MISMATCH_LIMIT BWN_PHY_OFDM(0x31)
#define BWN_PHY_CRS_ED_THRESH BWN_PHY_OFDM(0x32)
#define BWN_PHY_INPUT_PWRDB BWN_PHY_OFDM(0x34)
#define BWN_PHY_AFE_ADC_CTL_0 BWN_PHY_OFDM(0x36)
#define BWN_PHY_AFE_ADC_CTL_1 BWN_PHY_OFDM(0x37)
#define BWN_PHY_AFE_DAC_CTL BWN_PHY_OFDM(0x39)
#define BWN_PHY_AFE_CTL BWN_PHY_OFDM(0x3a)
#define BWN_PHY_AFE_CTL_OVR BWN_PHY_OFDM(0x3b)
#define BWN_PHY_AFE_CTL_OVRVAL BWN_PHY_OFDM(0x3c)
#define BWN_PHY_AFE_RSSI_CTL_0 BWN_PHY_OFDM(0x3d)
#define BWN_PHY_AFE_RSSI_CTL_1 BWN_PHY_OFDM(0x3e)
#define BWN_PHY_LP_PHY_CTL BWN_PHY_OFDM(0x48)
#define BWN_PHY_ENCORE BWN_PHY_OFDM(0x49)
#define BWN_PHY_RESET_CTL BWN_PHY_OFDM(0x4a)
#define BWN_PHY_RF_OVERRIDE_0 BWN_PHY_OFDM(0x4c)
#define BWN_PHY_RF_OVERRIDE_VAL_0 BWN_PHY_OFDM(0x4d)
#define BWN_PHY_TR_LOOKUP_1 BWN_PHY_OFDM(0x4e)
#define BWN_PHY_TR_LOOKUP_2 BWN_PHY_OFDM(0x4F)
#define BWN_PHY_LMS BWN_PHY_OFDM(0x55)
#define BWN_PHY_TABLE_ADDR BWN_PHY_OFDM(0x55) /* for LP */
#define BWN_PHY_TABLEDATALO BWN_PHY_OFDM(0x56)
#define BWN_PHY_TABLEDATAHI BWN_PHY_OFDM(0x57)
#define BWN_PHY_OFDM61 BWN_PHY_OFDM(0x61)
#define BWN_PHY_ADC_COMPENSATION_CTL BWN_PHY_OFDM(0x70)
#define BWN_PHY_OTABLECTL BWN_PHY_OFDM(0x72)
#define BWN_PHY_OTABLEI BWN_PHY_OFDM(0x73)
#define BWN_PHY_OTABLEQ BWN_PHY_OFDM(0x74)
#define BWN_PHY_HPWR_TSSICTL BWN_PHY_OFDM(0x78)
#define BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR BWN_PHY_OFDM(0x81)
#define BWN_PHY_IQ_NUM_SMPLS_ADDR BWN_PHY_OFDM(0x82)
#define BWN_PHY_IQ_ACC_HI_ADDR BWN_PHY_OFDM(0x83)
#define BWN_PHY_IQ_ACC_LO_ADDR BWN_PHY_OFDM(0x84)
#define BWN_PHY_IQ_I_PWR_ACC_HI_ADDR BWN_PHY_OFDM(0x85)
#define BWN_PHY_IQ_I_PWR_ACC_LO_ADDR BWN_PHY_OFDM(0x86)
#define BWN_PHY_IQ_Q_PWR_ACC_HI_ADDR BWN_PHY_OFDM(0x87)
#define BWN_PHY_IQ_Q_PWR_ACC_LO_ADDR BWN_PHY_OFDM(0x88)
#define BWN_PHY_ANTWRSETT BWN_PHY_OFDM(0x8c)
#define BWN_PHY_OFDM9B BWN_PHY_OFDM(0x9b)
#define BWN_PHY_A_PHY_CTL_ADDR BWN_PHY_OFDM(0x9c)
#define BWN_PHY_RX_COMP_COEFF_S BWN_PHY_OFDM(0x9e)
#define BWN_PHY_N1P1GAIN BWN_PHY_OFDM(0xa0)
#define BWN_PHY_SMPL_PLAY_COUNT BWN_PHY_OFDM(0xa0) /* for LP */
#define BWN_PHY_P1P2GAIN BWN_PHY_OFDM(0xa1)
#define BWN_PHY_SMPL_PLAY_BUFFER_CTL BWN_PHY_OFDM(0xA1) /* for LP */
#define BWN_PHY_N1N2GAIN BWN_PHY_OFDM(0xa2)
#define BWN_PHY_4WIRECTL BWN_PHY_OFDM(0xa2) /* for LP */
#define BWN_PHY_TX_PWR_CTL_CMD BWN_PHY_OFDM(0xa4)
#define BWN_PHY_CCKSHIFTBITS_WA BWN_PHY_OFDM(0xa5)
#define BWN_PHY_TX_PWR_CTL_NNUM BWN_PHY_OFDM(0xa5) /* for LP */
#define BWN_PHY_CCKSHIFTBITS BWN_PHY_OFDM(0xa7)
#define BWN_PHY_DIVSRCHIDX BWN_PHY_OFDM(0xa8)
#define BWN_PHY_DIVP1P2GAIN BWN_PHY_OFDM(0xab)
#define BWN_PHY_LP_RF_SIGNAL_LUT BWN_PHY_OFDM(0xac)
#define BWN_PHY_DIVSRCHGAINBACK BWN_PHY_OFDM(0xad)
#define BWN_PHY_RX_RADIO_CTL BWN_PHY_OFDM(0xae)
#define BWN_PHY_RF_OVERRIDE_2 BWN_PHY_OFDM(0xb0)
#define BWN_PHY_RF_OVERRIDE_2_VAL BWN_PHY_OFDM(0xb1)
#define BWN_PHY_PS_CTL_OVERRIDE_VAL0 BWN_PHY_OFDM(0xB2)
#define BWN_PHY_PS_CTL_OVERRIDE_VAL1 BWN_PHY_OFDM(0xB3)
#define BWN_PHY_PS_CTL_OVERRIDE_VAL2 BWN_PHY_OFDM(0xB4)
#define BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL BWN_PHY_OFDM(0xB5)
#define BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL BWN_PHY_OFDM(0xB6)
#define BWN_PHY_AFE_DDFS BWN_PHY_OFDM(0xb7)
#define BWN_PHY_AFE_DDFS_POINTER_INIT BWN_PHY_OFDM(0xB8)
#define BWN_PHY_AFE_DDFS_INCR_INIT BWN_PHY_OFDM(0xB9)
#define BWN_PHY_TR_LOOKUP_3 BWN_PHY_OFDM(0xbb)
#define BWN_PHY_TR_LOOKUP_4 BWN_PHY_OFDM(0xbc)
#define BWN_PHY_GPIO_OUTEN BWN_PHY_OFDM(0xbe)
#define BWN_PHY_GPIO_SELECT BWN_PHY_OFDM(0xbf)
#define BWN_PHY_CRSTHRES1 BWN_PHY_OFDM(0xc0)
#define BWN_PHY_CRSTHRES2 BWN_PHY_OFDM(0xc1)
#define BWN_PHY_4C3 BWN_PHY_OFDM(0xC3)
#define BWN_PHY_4C4 BWN_PHY_OFDM(0xC4)
#define BWN_PHY_4C5 BWN_PHY_OFDM(0xC5)
#define BWN_PHY_TR_LOOKUP_5 BWN_PHY_OFDM(0xC7)
#define BWN_PHY_TR_LOOKUP_6 BWN_PHY_OFDM(0xC8)
#define BWN_PHY_TR_LOOKUP_7 BWN_PHY_OFDM(0xC9)
#define BWN_PHY_TR_LOOKUP_8 BWN_PHY_OFDM(0xCA)
#define BWN_PHY_RF_PWR_OVERRIDE BWN_PHY_OFDM(0xd3)