sys/bus/u4b/serial/uchcom.c

183

static const struct uchcom_divider_record dividers[] =

sys/bus/u4b/serial/uchcom.c

539

for (i = 0; i != NELEM(dividers); i++) {

sys/bus/u4b/serial/uchcom.c

540

if (dividers[i].dvr_high >= rate &&

sys/bus/u4b/serial/uchcom.c

541

dividers[i].dvr_low <= rate) {

sys/bus/u4b/serial/uchcom.c

542

rp = &dividers[i];

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1016

struct atom_clock_dividers *dividers)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1023

memset(dividers, 0, sizeof(struct atom_clock_dividers));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1039

dividers->post_div = args.v3.ucPostDiv;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1040

dividers->enable_post_div = (args.v3.ucCntlFlag &

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1042

dividers->enable_dithen = (args.v3.ucCntlFlag &

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1044

dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1045

dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1046

dividers->ref_div = args.v3.ucRefDiv;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1047

dividers->vco_mode = (args.v3.ucCntlFlag &

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1059

dividers->post_div = args.v5.ucPostDiv;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1060

dividers->enable_post_div = (args.v5.ucCntlFlag &

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1062

dividers->enable_dithen = (args.v5.ucCntlFlag &

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1064

dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1065

dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1066

dividers->ref_div = args.v5.ucRefDiv;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1067

dividers->vco_mode = (args.v5.ucCntlFlag &

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1077

dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1078

dividers->real_clock = le32_to_cpu(args.v4.ulClock);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1088

dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1089

dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1090

dividers->ref_div = args.v6_out.ucPllRefDiv;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1091

dividers->post_div = args.v6_out.ucPllPostDiv;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1092

dividers->flags = args.v6_out.ucPllCntlFlag;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1093

dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1094

dividers->post_divider = args.v6_out.ulClock.ucPostDiv;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

161

struct atom_clock_dividers *dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2788

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2805

table->UvdLevel[count].VclkFrequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2809

table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2813

table->UvdLevel[count].DclkFrequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2817

table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2831

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2846

table->VceLevel[count].Frequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2850

table->VceLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2864

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2879

table->AcpLevel[count].Frequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2883

table->AcpLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2896

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2911

table->SamuLevel[count].Frequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2915

table->SamuLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3135

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3156

table->ACPILevel.SclkFrequency, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3160

table->ACPILevel.SclkDid = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3308

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3320

engine_clock, false, &dividers);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3324

reference_divider = 1 + dividers.ref_div;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3325

fbdiv = dividers.fb_div & 0x3FFFFFF;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3333

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3354

sclk->SclkDid = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/cik.c

1302

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/cik.c

1307

clock, false, &dividers);

sys/dev/drm/amd/amdgpu/cik.c

1314

tmp |= dividers.post_divider;

sys/dev/drm/amd/amdgpu/cik.c

1343

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/cik.c

1348

ecclk, false, &dividers);

sys/dev/drm/amd/amdgpu/cik.c

1363

tmp |= dividers.post_divider;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1001

pi->vce_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1041

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1061

table->entries[i].clk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1064

pi->samu_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1107

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1120

table->entries[i].clk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1123

pi->acp_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

666

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/kv_dpm.c

670

sclk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

674

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

907

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/kv_dpm.c

930

table->entries[i].vclk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

933

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

936

table->entries[i].dclk, false, &dividers);

sys/dev/drm/amd/amdgpu/kv_dpm.c

939

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

980

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/kv_dpm.c

998

table->entries[i].evclk, false, &dividers);

sys/dev/drm/amd/amdgpu/si_dpm.c

5249

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/si_dpm.c

5263

engine_clock, false, &dividers);

sys/dev/drm/amd/amdgpu/si_dpm.c

5267

reference_divider = 1 + dividers.ref_div;

sys/dev/drm/amd/amdgpu/si_dpm.c

5269

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/drm/amd/amdgpu/si_dpm.c

5274

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

sys/dev/drm/amd/amdgpu/si_dpm.c

5275

spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

sys/dev/drm/amd/amdgpu/si_dpm.c

5286

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/amd/amdgpu/si_dpm.c

7308

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/si_dpm.c

7371

0, false, &dividers);

sys/dev/drm/amd/amdgpu/si_dpm.c

7373

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/amd/amdgpu/vi.c

722

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/vi.c

727

clock, false, &dividers);

sys/dev/drm/amd/amdgpu/vi.c

738

tmp |= dividers.post_divider;

sys/dev/drm/amd/amdgpu/vi.c

792

struct atom_clock_dividers dividers;

sys/dev/drm/amd/amdgpu/vi.c

813

ecclk, false, &dividers);

sys/dev/drm/amd/amdgpu/vi.c

828

tmp |= dividers.post_divider;

sys/dev/drm/amd/display/modules/color/color_gamma.c

1069

struct dividers dividers)

sys/dev/drm/amd/display/modules/color/color_gamma.c

1092

p->r = dc_fixpt_div(p_last->r, dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1093

p->g = dc_fixpt_div(p_last->g, dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1094

p->b = dc_fixpt_div(p_last->b, dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1098

p->r = dc_fixpt_div(p_last->r, dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1099

p->g = dc_fixpt_div(p_last->g, dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1100

p->b = dc_fixpt_div(p_last->b, dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1104

p->r = dc_fixpt_div(p_last->r, dividers.divider3);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1105

p->g = dc_fixpt_div(p_last->g, dividers.divider3);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1106

p->b = dc_fixpt_div(p_last->b, dividers.divider3);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1362

struct dividers dividers;

sys/dev/drm/amd/display/modules/color/color_gamma.c

1401

dividers.divider1 = dc_fixpt_from_fraction(3, 2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1402

dividers.divider2 = dc_fixpt_from_int(2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1403

dividers.divider3 = dc_fixpt_from_fraction(5, 2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1410

dividers);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1413

scale_gamma(rgb_user, ramp, dividers);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1415

scale_gamma_dx(rgb_user, ramp, dividers);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1512

struct dividers dividers;

sys/dev/drm/amd/display/modules/color/color_gamma.c

1535

dividers.divider1 = dc_fixpt_from_fraction(3, 2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1536

dividers.divider2 = dc_fixpt_from_int(2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1537

dividers.divider3 = dc_fixpt_from_fraction(5, 2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1539

scale_user_regamma_ramp(rgb_user, &regamma->ramp, dividers);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1572

struct dividers dividers;

sys/dev/drm/amd/display/modules/color/color_gamma.c

1611

dividers.divider1 = dc_fixpt_from_fraction(3, 2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1612

dividers.divider2 = dc_fixpt_from_int(2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1613

dividers.divider3 = dc_fixpt_from_fraction(5, 2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1620

dividers);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1623

scale_gamma(rgb_user, ramp, dividers);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1625

scale_gamma_dx(rgb_user, ramp, dividers);

sys/dev/drm/amd/display/modules/color/color_gamma.c

795

struct dividers dividers)

sys/dev/drm/amd/display/modules/color/color_gamma.c

831

dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

833

dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

835

dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

840

dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

842

dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

844

dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

849

dividers.divider3);

sys/dev/drm/amd/display/modules/color/color_gamma.c

851

dividers.divider3);

sys/dev/drm/amd/display/modules/color/color_gamma.c

853

dividers.divider3);

sys/dev/drm/amd/display/modules/color/color_gamma.c

858

struct dividers dividers)

sys/dev/drm/amd/display/modules/color/color_gamma.c

926

struct dividers dividers)

sys/dev/drm/amd/display/modules/color/color_gamma.c

960

dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

962

dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

964

dividers.divider1);

sys/dev/drm/amd/display/modules/color/color_gamma.c

969

dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

971

dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

973

dividers.divider2);

sys/dev/drm/amd/display/modules/color/color_gamma.c

978

dividers.divider3);

sys/dev/drm/amd/display/modules/color/color_gamma.c

980

dividers.divider3);

sys/dev/drm/amd/display/modules/color/color_gamma.c

982

dividers.divider3);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

351

pp_atomctrl_clock_dividers_kong *dividers)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

364

dividers->pll_post_divider = pll_parameters.ucPostDiv;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

365

dividers->real_clock = le32_to_cpu(pll_parameters.ulClock);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

374

pp_atomctrl_clock_dividers_vi *dividers)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

388

dividers->pll_post_divider =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

390

dividers->real_clock =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

393

dividers->ul_fb_div.ul_fb_div_frac =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

395

dividers->ul_fb_div.ul_fb_div =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

398

dividers->uc_pll_ref_div =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

400

dividers->uc_pll_post_div =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

402

dividers->uc_pll_cntl_flag =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

411

pp_atomctrl_clock_dividers_ai *dividers)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

425

dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

426

dividers->usSclk_fcw_int = le16_to_cpu(pll_patameters.usSclk_fcw_int);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

427

dividers->ucSclkPostDiv = pll_patameters.ucSclkPostDiv;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

428

dividers->ucSclkVcoMode = pll_patameters.ucSclkVcoMode;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

429

dividers->ucSclkPllRange = pll_patameters.ucSclkPllRange;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

430

dividers->ucSscEnable = pll_patameters.ucSscEnable;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

431

dividers->usSsc_fcw1_frac = le16_to_cpu(pll_patameters.usSsc_fcw1_frac);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

432

dividers->usSsc_fcw1_int = le16_to_cpu(pll_patameters.usSsc_fcw1_int);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

433

dividers->usPcc_fcw_int = le16_to_cpu(pll_patameters.usPcc_fcw_int);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

434

dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

435

dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

443

pp_atomctrl_clock_dividers_vi *dividers)

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

458

dividers->pll_post_divider =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

460

dividers->real_clock =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

463

dividers->ul_fb_div.ul_fb_div_frac =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

465

dividers->ul_fb_div.ul_fb_div =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

468

dividers->uc_pll_ref_div =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

470

dividers->uc_pll_post_div =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

472

dividers->uc_pll_cntl_flag =

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

300

extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

301

extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

310

pp_atomctrl_clock_dividers_kong *dividers);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

315

extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

248

struct pp_atomfwctrl_clock_dividers_soc15 *dividers)

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

266

dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

267

dividers->ulDid = le32_to_cpu(pll_output->dfs_did);

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

268

dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

269

dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

270

dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

271

dividers->ucPll_ss_enable = pll_output->pll_ss_enable;

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.h

219

struct pp_atomfwctrl_clock_dividers_soc15 *dividers);

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

441

pp_atomctrl_clock_dividers_kong dividers;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

486

&dividers);

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

489

(uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

503

&dividers);

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

506

(uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

517

&dividers);

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

520

(uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

529

&dividers);

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

532

(uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

543

&dividers);

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

546

(uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1457

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1462

lclock, &dividers),

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1466

*curr_lclk_did = dividers.ulDid;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1525

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1554

gfx_clock, &dividers),

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1560

cpu_to_le32(dividers.ulPll_fb_mult);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1562

current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1564

cpu_to_le32(dividers.ulPll_ss_fbsmult);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1566

cpu_to_le16(dividers.usPll_ss_slew_frac);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1567

current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1590

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1614

soc_clock, &dividers),

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1618

*current_soc_did = (uint8_t)dividers.ulDid;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1726

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1754

hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1762

current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1763

current_memclk_level->Did = (uint8_t)(dividers.ulDid);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1897

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1902

eclock, &dividers),

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1906

*current_eclk_did = (uint8_t)dividers.ulDid;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1950

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1954

vclock, &dividers),

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1958

*current_vclk_did = (uint8_t)dividers.ulDid;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1966

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1970

dclock, &dividers),

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

1974

*current_dclk_did = (uint8_t)dividers.ulDid;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1380

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1403

table->ACPILevel.SclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1409

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1521

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1537

table->UvdLevel[count].VclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1541

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1544

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1548

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1562

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1576

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1581

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1594

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1607

table->AcpLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1611

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

299

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

311

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

319

ref_divider = 1 + dividers.uc_pll_ref_div;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

322

fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

326

SPLL_REF_DIV, dividers.uc_pll_ref_div);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

328

SPLL_PDIV_A, dividers.uc_pll_post_div);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

341

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

364

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1307

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1338

table->ACPILevel.SclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1343

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1427

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1448

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1453

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1466

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1485

table->AcpLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1489

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1563

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1584

table->UvdLevel[count].VclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1588

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1591

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1595

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

861

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

873

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

881

ref_divider = 1 + dividers.uc_pll_ref_div;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

884

fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

888

SPLL_REF_DIV, dividers.uc_pll_ref_div);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

890

SPLL_PDIV_A, dividers.uc_pll_post_div);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

904

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

933

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1427

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1451

table->ACPILevel.SclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1457

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

799

pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

811

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

819

reference_divider = 1 + dividers.uc_pll_ref_div;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

822

fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

826

CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

828

CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

842

uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

868

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1290

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1322

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1327

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1396

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1427

table->UvdLevel[count].VclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1431

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1434

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1438

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1776

pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1934

result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1938

table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1940

table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

845

struct pp_atomctrl_clock_dividers_ai dividers;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

854

result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

856

sclk_setting->Fcw_int = dividers.usSclk_fcw_int;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

857

sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

858

sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

859

sclk_setting->PllRange = dividers.ucSclkPllRange;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

861

sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

863

sclk_setting->SSc_En = dividers.ucSscEnable;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

864

sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

865

sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

866

sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1180

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1199

table->ACPILevel.SclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1206

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1313

pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1342

&dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1348

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1351

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1357

(uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1373

pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1400

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1405

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1418

pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1445

table->AcpLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1449

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

541

pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

553

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

561

reference_divider = 1 + dividers.uc_pll_ref_div;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

564

fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

568

CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

570

CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

584

uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

610

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1209

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1241

table->VceLevel[count].Frequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1246

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1322

struct pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1353

table->UvdLevel[count].VclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1357

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1360

table->UvdLevel[count].DclkFrequency, &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1364

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1937

pp_atomctrl_clock_dividers_vi dividers;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2112

smu_data->bif_sclk_table[i], &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2119

PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2122

PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

722

struct pp_atomctrl_clock_dividers_ai dividers;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

731

result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

733

sclk_setting->Fcw_int = dividers.usSclk_fcw_int;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

734

sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

735

sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

736

sclk_setting->PllRange = dividers.ucSclkPllRange;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

738

sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

740

sclk_setting->SSc_En = dividers.ucSscEnable;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

741

sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

742

sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

743

sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;

sys/dev/drm/i915/intel_dpll_mgr.c

1246

} dividers[] = {

sys/dev/drm/i915/intel_dpll_mgr.c

1256

for (d = 0; d < ARRAY_SIZE(dividers); d++) {

sys/dev/drm/i915/intel_dpll_mgr.c

1258

for (i = 0; i < dividers[d].n_dividers; i++) {

sys/dev/drm/i915/intel_dpll_mgr.c

1259

unsigned int p = dividers[d].list[i];

sys/dev/drm/i915/intel_dpll_mgr.c

2239

static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,

sys/dev/drm/i915/intel_dpll_mgr.c

2249

for (d = 0; d < ARRAY_SIZE(dividers); d++) {

sys/dev/drm/i915/intel_dpll_mgr.c

2250

dco = afe_clock * dividers[d];

sys/dev/drm/i915/intel_dpll_mgr.c

2257

best_div = dividers[d];

sys/dev/drm/radeon/btc_dpm.c

2553

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/btc_dpm.c

2603

0, false, &dividers);

sys/dev/drm/radeon/btc_dpm.c

2605

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/ci_dpm.c

2686

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ci_dpm.c

2703

table->UvdLevel[count].VclkFrequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2707

table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2711

table->UvdLevel[count].DclkFrequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2715

table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2729

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ci_dpm.c

2744

table->VceLevel[count].Frequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2748

table->VceLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2762

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ci_dpm.c

2777

table->AcpLevel[count].Frequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2781

table->AcpLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2794

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ci_dpm.c

2809

table->SamuLevel[count].Frequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

2813

table->SamuLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

3027

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ci_dpm.c

3048

table->ACPILevel.SclkFrequency, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

3052

table->ACPILevel.SclkDid = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

3198

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ci_dpm.c

3210

engine_clock, false, &dividers);

sys/dev/drm/radeon/ci_dpm.c

3214

reference_divider = 1 + dividers.ref_div;

sys/dev/drm/radeon/ci_dpm.c

3215

fbdiv = dividers.fb_div & 0x3FFFFFF;

sys/dev/drm/radeon/ci_dpm.c

3223

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/radeon/ci_dpm.c

3244

sclk->SclkDid = (u8)dividers.post_divider;

sys/dev/drm/radeon/cik.c

9445

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/cik.c

9449

clock, false, &dividers);

sys/dev/drm/radeon/cik.c

9455

tmp |= dividers.post_divider;

sys/dev/drm/radeon/cik.c

9484

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/cik.c

9488

ecclk, false, &dividers);

sys/dev/drm/radeon/cik.c

9502

tmp |= dividers.post_divider;

sys/dev/drm/radeon/cypress_dpm.c

2029

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/cypress_dpm.c

2060

0, false, &dividers);

sys/dev/drm/radeon/cypress_dpm.c

2062

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/cypress_dpm.c

494

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/cypress_dpm.c

501

memory_clock, strobe_mode, &dividers);

sys/dev/drm/radeon/cypress_dpm.c

509

dividers.post_div = 1;

sys/dev/drm/radeon/cypress_dpm.c

512

ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);

sys/dev/drm/radeon/cypress_dpm.c

519

mpll_ad_func_cntl |= CLKR(dividers.ref_div);

sys/dev/drm/radeon/cypress_dpm.c

520

mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);

sys/dev/drm/radeon/cypress_dpm.c

521

mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);

sys/dev/drm/radeon/cypress_dpm.c

522

mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);

sys/dev/drm/radeon/cypress_dpm.c

525

if (dividers.vco_mode)

sys/dev/drm/radeon/cypress_dpm.c

536

mpll_dq_func_cntl |= CLKR(dividers.ref_div);

sys/dev/drm/radeon/cypress_dpm.c

537

mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);

sys/dev/drm/radeon/cypress_dpm.c

538

mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);

sys/dev/drm/radeon/cypress_dpm.c

539

mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);

sys/dev/drm/radeon/cypress_dpm.c

547

if (dividers.vco_mode)

sys/dev/drm/radeon/cypress_dpm.c

555

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/drm/radeon/cypress_dpm.c

560

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/drm/radeon/cypress_dpm.c

567

(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);

sys/dev/drm/radeon/evergreen.c

1131

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/evergreen.c

1134

clock, false, &dividers);

sys/dev/drm/radeon/evergreen.c

1138

WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));

sys/dev/drm/radeon/kv_dpm.c

1019

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/kv_dpm.c

1032

table->entries[i].clk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

1035

pi->acp_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

534

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/kv_dpm.c

538

sclk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

542

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

819

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/kv_dpm.c

842

table->entries[i].vclk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

845

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

848

table->entries[i].dclk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

851

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

892

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/kv_dpm.c

910

table->entries[i].evclk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

913

pi->vce_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

953

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/kv_dpm.c

973

table->entries[i].clk, false, &dividers);

sys/dev/drm/radeon/kv_dpm.c

976

pi->samu_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/ni.c

2735

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ni.c

2739

ecclk, false, &dividers);

sys/dev/drm/radeon/ni.c

2751

WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));

sys/dev/drm/radeon/ni_dpm.c

2002

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ni_dpm.c

2016

engine_clock, false, &dividers);

sys/dev/drm/radeon/ni_dpm.c

2020

reference_divider = 1 + dividers.ref_div;

sys/dev/drm/radeon/ni_dpm.c

2023

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;

sys/dev/drm/radeon/ni_dpm.c

2028

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

sys/dev/drm/radeon/ni_dpm.c

2029

spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

sys/dev/drm/radeon/ni_dpm.c

2040

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/radeon/ni_dpm.c

2175

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ni_dpm.c

2182

memory_clock, strobe_mode, &dividers);

sys/dev/drm/radeon/ni_dpm.c

2190

dividers.post_div = 1;

sys/dev/drm/radeon/ni_dpm.c

2193

ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);

sys/dev/drm/radeon/ni_dpm.c

2200

mpll_ad_func_cntl |= CLKR(dividers.ref_div);

sys/dev/drm/radeon/ni_dpm.c

2201

mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);

sys/dev/drm/radeon/ni_dpm.c

2202

mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);

sys/dev/drm/radeon/ni_dpm.c

2203

mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);

sys/dev/drm/radeon/ni_dpm.c

2206

if (dividers.vco_mode)

sys/dev/drm/radeon/ni_dpm.c

2217

mpll_dq_func_cntl |= CLKR(dividers.ref_div);

sys/dev/drm/radeon/ni_dpm.c

2218

mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);

sys/dev/drm/radeon/ni_dpm.c

2219

mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);

sys/dev/drm/radeon/ni_dpm.c

2220

mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);

sys/dev/drm/radeon/ni_dpm.c

2228

if (dividers.vco_mode)

sys/dev/drm/radeon/ni_dpm.c

2236

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/drm/radeon/ni_dpm.c

2241

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/drm/radeon/ni_dpm.c

2248

(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);

sys/dev/drm/radeon/ni_dpm.c

4050

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/ni_dpm.c

4103

0, false, &dividers);

sys/dev/drm/radeon/ni_dpm.c

4105

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/radeon.h

300

struct atom_clock_dividers *dividers);

sys/dev/drm/radeon/radeon_atombios.c

2831

struct atom_clock_dividers *dividers)

sys/dev/drm/radeon/radeon_atombios.c

2838

memset(dividers, 0, sizeof(struct atom_clock_dividers));

sys/dev/drm/radeon/radeon_atombios.c

2851

dividers->post_div = args.v1.ucPostDiv;

sys/dev/drm/radeon/radeon_atombios.c

2852

dividers->fb_div = args.v1.ucFbDiv;

sys/dev/drm/radeon/radeon_atombios.c

2853

dividers->enable_post_div = true;

sys/dev/drm/radeon/radeon_atombios.c

2865

dividers->post_div = args.v2.ucPostDiv;

sys/dev/drm/radeon/radeon_atombios.c

2866

dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);

sys/dev/drm/radeon/radeon_atombios.c

2867

dividers->ref_div = args.v2.ucAction;

sys/dev/drm/radeon/radeon_atombios.c

2869

dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?

sys/dev/drm/radeon/radeon_atombios.c

2871

dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;

sys/dev/drm/radeon/radeon_atombios.c

2873

dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;

sys/dev/drm/radeon/radeon_atombios.c

2880

dividers->post_div = args.v3.ucPostDiv;

sys/dev/drm/radeon/radeon_atombios.c

2881

dividers->enable_post_div = (args.v3.ucCntlFlag &

sys/dev/drm/radeon/radeon_atombios.c

2883

dividers->enable_dithen = (args.v3.ucCntlFlag &

sys/dev/drm/radeon/radeon_atombios.c

2885

dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);

sys/dev/drm/radeon/radeon_atombios.c

2886

dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);

sys/dev/drm/radeon/radeon_atombios.c

2887

dividers->ref_div = args.v3.ucRefDiv;

sys/dev/drm/radeon/radeon_atombios.c

2888

dividers->vco_mode = (args.v3.ucCntlFlag &

sys/dev/drm/radeon/radeon_atombios.c

2900

dividers->post_div = args.v5.ucPostDiv;

sys/dev/drm/radeon/radeon_atombios.c

2901

dividers->enable_post_div = (args.v5.ucCntlFlag &

sys/dev/drm/radeon/radeon_atombios.c

2903

dividers->enable_dithen = (args.v5.ucCntlFlag &

sys/dev/drm/radeon/radeon_atombios.c

2905

dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);

sys/dev/drm/radeon/radeon_atombios.c

2906

dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);

sys/dev/drm/radeon/radeon_atombios.c

2907

dividers->ref_div = args.v5.ucRefDiv;

sys/dev/drm/radeon/radeon_atombios.c

2908

dividers->vco_mode = (args.v5.ucCntlFlag &

sys/dev/drm/radeon/radeon_atombios.c

2919

dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;

sys/dev/drm/radeon/radeon_atombios.c

2920

dividers->real_clock = le32_to_cpu(args.v4.ulClock);

sys/dev/drm/radeon/radeon_atombios.c

2930

dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);

sys/dev/drm/radeon/radeon_atombios.c

2931

dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);

sys/dev/drm/radeon/radeon_atombios.c

2932

dividers->ref_div = args.v6_out.ucPllRefDiv;

sys/dev/drm/radeon/radeon_atombios.c

2933

dividers->post_div = args.v6_out.ucPllPostDiv;

sys/dev/drm/radeon/radeon_atombios.c

2934

dividers->flags = args.v6_out.ucPllCntlFlag;

sys/dev/drm/radeon/radeon_atombios.c

2935

dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);

sys/dev/drm/radeon/radeon_atombios.c

2936

dividers->post_divider = args.v6_out.ulClock.ucPostDiv;

sys/dev/drm/radeon/rs780_dpm.c

1032

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rs780_dpm.c

1043

ps->sclk_high, false, &dividers);

sys/dev/drm/radeon/rs780_dpm.c

1047

rs780_force_fbdiv(rdev, dividers.fb_div);

sys/dev/drm/radeon/rs780_dpm.c

1050

ps->sclk_low, false, &dividers);

sys/dev/drm/radeon/rs780_dpm.c

1054

rs780_force_fbdiv(rdev, dividers.fb_div);

sys/dev/drm/radeon/rs780_dpm.c

77

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rs780_dpm.c

82

default_state->sclk_low, false, &dividers);

sys/dev/drm/radeon/rs780_dpm.c

86

r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);

sys/dev/drm/radeon/rs780_dpm.c

87

r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);

sys/dev/drm/radeon/rs780_dpm.c

88

r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);

sys/dev/drm/radeon/rs780_dpm.c

90

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv6xx_dpm.c

143

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv6xx_dpm.c

146

clock, false, &dividers);

sys/dev/drm/radeon/rv6xx_dpm.c

150

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv6xx_dpm.c

151

step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);

sys/dev/drm/radeon/rv6xx_dpm.c

1935

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv6xx_dpm.c

1958

0, false, &dividers);

sys/dev/drm/radeon/rv6xx_dpm.c

1960

pi->spll_ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/rv6xx_dpm.c

1965

0, false, &dividers);

sys/dev/drm/radeon/rv6xx_dpm.c

1967

pi->mpll_ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/rv6xx_dpm.c

527

struct atom_clock_dividers *dividers,

sys/dev/drm/radeon/rv6xx_dpm.c

530

return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /

sys/dev/drm/radeon/rv6xx_dpm.c

531

(dividers->ref_div + 1);

sys/dev/drm/radeon/rv6xx_dpm.c

554

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv6xx_dpm.c

561

if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) {

sys/dev/drm/radeon/rv6xx_dpm.c

562

vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers,

sys/dev/drm/radeon/rv6xx_dpm.c

568

(ref_clk / (dividers.ref_div + 1)),

sys/dev/drm/radeon/rv6xx_dpm.c

574

(ref_clk / (dividers.ref_div + 1)));

sys/dev/drm/radeon/rv6xx_dpm.c

601

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv6xx_dpm.c

603

if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, &dividers))

sys/dev/drm/radeon/rv6xx_dpm.c

607

rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);

sys/dev/drm/radeon/rv6xx_dpm.c

608

rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);

sys/dev/drm/radeon/rv6xx_dpm.c

609

rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);

sys/dev/drm/radeon/rv6xx_dpm.c

611

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv6xx_dpm.c

634

struct atom_clock_dividers *dividers,

sys/dev/drm/radeon/rv6xx_dpm.c

647

*dividers = req_dividers;

sys/dev/drm/radeon/rv6xx_dpm.c

657

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv6xx_dpm.c

667

&dividers,

sys/dev/drm/radeon/rv6xx_dpm.c

673

&dividers,

sys/dev/drm/radeon/rv6xx_dpm.c

679

&dividers,

sys/dev/drm/radeon/rv6xx_dpm.c

686

(ref_clk / (dividers.ref_div + 1)),

sys/dev/drm/radeon/rv6xx_dpm.c

692

(ref_clk / (dividers.ref_div + 1)));

sys/dev/drm/radeon/rv730_dpm.c

131

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv730_dpm.c

136

memory_clock, false, &dividers);

sys/dev/drm/radeon/rv730_dpm.c

140

reference_divider = dividers.ref_div + 1;

sys/dev/drm/radeon/rv730_dpm.c

142

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv730_dpm.c

143

post_divider = ((dividers.post_div >> 4) & 0xf) +

sys/dev/drm/radeon/rv730_dpm.c

144

(dividers.post_div & 0xf) + 2;

sys/dev/drm/radeon/rv730_dpm.c

149

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv730_dpm.c

155

mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);

sys/dev/drm/radeon/rv730_dpm.c

156

mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf);

sys/dev/drm/radeon/rv730_dpm.c

157

mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf);

sys/dev/drm/radeon/rv730_dpm.c

160

mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);

sys/dev/drm/radeon/rv730_dpm.c

161

if (dividers.enable_dithen)

sys/dev/drm/radeon/rv730_dpm.c

174

u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);

sys/dev/drm/radeon/rv730_dpm.c

45

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv730_dpm.c

58

engine_clock, false, &dividers);

sys/dev/drm/radeon/rv730_dpm.c

62

reference_divider = 1 + dividers.ref_div;

sys/dev/drm/radeon/rv730_dpm.c

64

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv730_dpm.c

65

post_divider = ((dividers.post_div >> 4) & 0xf) +

sys/dev/drm/radeon/rv730_dpm.c

66

(dividers.post_div & 0xf) + 2;

sys/dev/drm/radeon/rv730_dpm.c

75

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv730_dpm.c

80

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

sys/dev/drm/radeon/rv730_dpm.c

81

spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);

sys/dev/drm/radeon/rv730_dpm.c

82

spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);

sys/dev/drm/radeon/rv740_dpm.c

125

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv740_dpm.c

138

engine_clock, false, &dividers);

sys/dev/drm/radeon/rv740_dpm.c

142

reference_divider = 1 + dividers.ref_div;

sys/dev/drm/radeon/rv740_dpm.c

144

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/drm/radeon/rv740_dpm.c

149

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

sys/dev/drm/radeon/rv740_dpm.c

150

spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

sys/dev/drm/radeon/rv740_dpm.c

161

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/radeon/rv740_dpm.c

200

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv740_dpm.c

206

memory_clock, false, &dividers);

sys/dev/drm/radeon/rv740_dpm.c

210

ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div);

sys/dev/drm/radeon/rv740_dpm.c

217

mpll_ad_func_cntl |= CLKR(dividers.ref_div);

sys/dev/drm/radeon/rv740_dpm.c

218

mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);

sys/dev/drm/radeon/rv740_dpm.c

219

mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);

sys/dev/drm/radeon/rv740_dpm.c

220

mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);

sys/dev/drm/radeon/rv740_dpm.c

223

if (dividers.vco_mode)

sys/dev/drm/radeon/rv740_dpm.c

234

mpll_dq_func_cntl |= CLKR(dividers.ref_div);

sys/dev/drm/radeon/rv740_dpm.c

235

mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);

sys/dev/drm/radeon/rv740_dpm.c

236

mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);

sys/dev/drm/radeon/rv740_dpm.c

237

mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);

sys/dev/drm/radeon/rv740_dpm.c

240

if (dividers.vco_mode)

sys/dev/drm/radeon/rv740_dpm.c

248

u32 vco_freq = memory_clock * dividers.post_div;

sys/dev/drm/radeon/rv740_dpm.c

253

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

sys/dev/drm/radeon/rv740_dpm.c

260

(dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);

sys/dev/drm/radeon/rv770_dpm.c

2350

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv770_dpm.c

2378

0, false, &dividers);

sys/dev/drm/radeon/rv770_dpm.c

2380

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/rv770_dpm.c

325

struct atom_clock_dividers *dividers,

sys/dev/drm/radeon/rv770_dpm.c

337

post_divider = dividers->post_div;

sys/dev/drm/radeon/rv770_dpm.c

338

reference_divider = dividers->ref_div;

sys/dev/drm/radeon/rv770_dpm.c

407

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv770_dpm.c

415

memory_clock, false, &dividers);

sys/dev/drm/radeon/rv770_dpm.c

419

if ((dividers.ref_div < 1) || (dividers.ref_div > 5))

sys/dev/drm/radeon/rv770_dpm.c

424

&dividers, &clkf, &clkfrac);

sys/dev/drm/radeon/rv770_dpm.c

426

ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);

sys/dev/drm/radeon/rv770_dpm.c

437

mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);

sys/dev/drm/radeon/rv770_dpm.c

443

if (dividers.vco_mode)

sys/dev/drm/radeon/rv770_dpm.c

452

&dividers, &clkf, &clkfrac);

sys/dev/drm/radeon/rv770_dpm.c

456

ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);

sys/dev/drm/radeon/rv770_dpm.c

465

mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);

sys/dev/drm/radeon/rv770_dpm.c

471

if (dividers.vco_mode)

sys/dev/drm/radeon/rv770_dpm.c

493

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/rv770_dpm.c

511

engine_clock, false, &dividers);

sys/dev/drm/radeon/rv770_dpm.c

515

reference_divider = 1 + dividers.ref_div;

sys/dev/drm/radeon/rv770_dpm.c

517

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv770_dpm.c

518

post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2;

sys/dev/drm/radeon/rv770_dpm.c

526

if (dividers.enable_post_div)

sys/dev/drm/radeon/rv770_dpm.c

531

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

sys/dev/drm/radeon/rv770_dpm.c

532

spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);

sys/dev/drm/radeon/rv770_dpm.c

533

spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);

sys/dev/drm/radeon/si_dpm.c

4790

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/si_dpm.c

4804

engine_clock, false, &dividers);

sys/dev/drm/radeon/si_dpm.c

4808

reference_divider = 1 + dividers.ref_div;

sys/dev/drm/radeon/si_dpm.c

4810

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

sys/dev/drm/radeon/si_dpm.c

4815

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

sys/dev/drm/radeon/si_dpm.c

4816

spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

sys/dev/drm/radeon/si_dpm.c

4827

u32 vco_freq = engine_clock * dividers.post_div;

sys/dev/drm/radeon/si_dpm.c

6905

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/si_dpm.c

6983

0, false, &dividers);

sys/dev/drm/radeon/si_dpm.c

6985

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/sumo_dpm.c

554

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/sumo_dpm.c

558

pl->sclk, false, &dividers);

sys/dev/drm/radeon/sumo_dpm.c

562

sumo_set_divider_value(rdev, index, dividers.post_div);

sys/dev/drm/radeon/sumo_dpm.c

789

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/sumo_dpm.c

794

false, &dividers);

sys/dev/drm/radeon/sumo_dpm.c

798

WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);

sys/dev/drm/radeon/trinity_dpm.c

372

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/trinity_dpm.c

379

25000, false, &dividers);

sys/dev/drm/radeon/trinity_dpm.c

387

value |= PDS_DIV(dividers.post_div);

sys/dev/drm/radeon/trinity_dpm.c

591

struct atom_clock_dividers dividers;

sys/dev/drm/radeon/trinity_dpm.c

597

sclk, false, &dividers);

sys/dev/drm/radeon/trinity_dpm.c

603

value |= CLK_DIVIDER(dividers.post_div);

sys/dev/drm/radeon/trinity_dpm.c

607

sclk/2, false, &dividers);

sys/dev/drm/radeon/trinity_dpm.c

613

value |= PD_SCLK_DIVIDER(dividers.post_div);