stand/boot/efi/boot1/boot_module.h

54

struct dev_info *next;

sys/dev/drm/amd/amdgpu/amdgpu_acp.c

173

dev_info(dev, "device %s added to pm domain\n", auto_dev_name);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

84

dev_info(adev->dev, "kfd not supported on this ASIC\n");

sys/dev/drm/amd/amdgpu/amdgpu_device.c

3256

dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");

sys/dev/drm/amd/amdgpu/amdgpu_device.c

3393

dev_info(adev->dev, "GPU reset begin!\n");

sys/dev/drm/amd/amdgpu/amdgpu_device.c

3452

dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));

sys/dev/drm/amd/amdgpu/amdgpu_device.c

3455

dev_info(adev->dev, "GPU reset(%d) succeeded!\n",atomic_read(&adev->gpu_reset_counter));

sys/dev/drm/amd/amdgpu/amdgpu_gmc.c

129

dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",

sys/dev/drm/amd/amdgpu/amdgpu_gmc.c

173

dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",

sys/dev/drm/amd/amdgpu/amdgpu_gmc.c

213

dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

153

dev_info(dev->dev,

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

155

dev_info(dev->dev,

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

170

dev_info(dev->dev,

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

172

dev_info(dev->dev,

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

687

struct drm_amdgpu_info_device dev_info = {};

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

690

dev_info.device_id = dev->pdev->device;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

691

dev_info.chip_rev = adev->rev_id;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

692

dev_info.external_rev = adev->external_rev_id;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

693

dev_info.pci_rev = dev->pdev->revision;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

694

dev_info.family = adev->family;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

695

dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

696

dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

698

dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

700

dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

701

dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

703

dev_info.max_engine_clock = adev->clock.default_sclk * 10;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

704

dev_info.max_memory_clock = adev->clock.default_mclk * 10;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

706

dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

707

dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

709

dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

710

dev_info._pad = 0;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

711

dev_info.ids_flags = 0;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

713

dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

715

dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

725

dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

726

dev_info.virtual_address_max =

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

730

dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

731

dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

733

dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

734

dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

735

dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

736

dev_info.cu_active_number = adev->gfx.cu_info.number;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

737

dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

738

dev_info.ce_ram_size = adev->gfx.ce_ram_size;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

739

memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

741

memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

743

dev_info.vram_type = adev->gmc.vram_type;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

744

dev_info.vram_bit_width = adev->gmc.vram_width;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

745

dev_info.vce_harvest_config = adev->vce.harvest_config;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

746

dev_info.gc_double_offchip_lds_buf =

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

750

dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

751

dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

752

dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

753

dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

754

dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

755

dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

756

dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

757

dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

759

dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

760

dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

761

dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

762

dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

763

dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

764

dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

765

dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

767

return copy_to_user(out, &dev_info,

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

768

min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;

sys/dev/drm/amd/amdgpu/amdgpu_xgmi.c

110

dev_info(adev->dev, "XGMI: Add node %d to hive 0x%llx.\n",

sys/dev/drm/amd/amdgpu/cik.c

1240

dev_info(adev->dev, "GPU pci config reset\n");

sys/dev/drm/amd/amdgpu/cik_ih.c

416

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1109

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/cz_ih.c

395

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2929

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3055

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2817

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4745

dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4759

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5129

dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5143

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3524

dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1224

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1387

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

744

dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",

sys/dev/drm/amd/amdgpu/iceland_ih.c

395

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1001

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1336

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/soc15.c

395

dev_info(adev->dev, "GPU reset\n");

sys/dev/drm/amd/amdgpu/tonga_ih.c

458

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1186

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1507

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

665

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

750

dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/amd/amdgpu/vi.c

669

dev_info(adev->dev, "GPU pci config reset\n");

sys/dev/drm/drm_fb_helper.c

2755

dev_info(dev->dev, "fb%d: %s frame buffer device\n",

sys/dev/drm/drm_print.c

143

dev_info(p->arg, "[" DRM_NAME "]");

sys/dev/drm/i915/i915_gem_gtt.c

3438

dev_info(dev_priv->drm.dev,

sys/dev/drm/i915/intel_uc.c

410

dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",

sys/dev/drm/i915/intel_uc.c

412

dev_info(i915->drm.dev, "GuC submission %s\n",

sys/dev/drm/i915/intel_uc.c

414

dev_info(i915->drm.dev, "HuC %s\n",

sys/dev/drm/i915/intel_uncore.c

686

dev_info(dev_priv->drm.dev,

sys/dev/drm/radeon/cik.c

4821

dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",

sys/dev/drm/radeon/cik.c

4823

dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",

sys/dev/drm/radeon/cik.c

4825

dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",

sys/dev/drm/radeon/cik.c

4827

dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",

sys/dev/drm/radeon/cik.c

4829

dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",

sys/dev/drm/radeon/cik.c

4831

dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",

sys/dev/drm/radeon/cik.c

4833

dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",

sys/dev/drm/radeon/cik.c

4835

dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",

sys/dev/drm/radeon/cik.c

4837

dev_info(rdev->dev, " SDMA0_STATUS_REG = 0x%08X\n",

sys/dev/drm/radeon/cik.c

4839

dev_info(rdev->dev, " SDMA1_STATUS_REG = 0x%08X\n",

sys/dev/drm/radeon/cik.c

4841

dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));

sys/dev/drm/radeon/cik.c

4842

dev_info(rdev->dev, " CP_STALLED_STAT1 = 0x%08x\n",

sys/dev/drm/radeon/cik.c

4844

dev_info(rdev->dev, " CP_STALLED_STAT2 = 0x%08x\n",

sys/dev/drm/radeon/cik.c

4846

dev_info(rdev->dev, " CP_STALLED_STAT3 = 0x%08x\n",

sys/dev/drm/radeon/cik.c

4848

dev_info(rdev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",

sys/dev/drm/radeon/cik.c

4850

dev_info(rdev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",

sys/dev/drm/radeon/cik.c

4852

dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));

sys/dev/drm/radeon/cik.c

4853

dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));

sys/dev/drm/radeon/cik.c

4854

dev_info(rdev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",

sys/dev/drm/radeon/cik.c

4856

dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));

sys/dev/drm/radeon/cik.c

4957

dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

sys/dev/drm/radeon/cik.c

4960

dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",

sys/dev/drm/radeon/cik.c

4962

dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

sys/dev/drm/radeon/cik.c

5037

dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/cik.c

5051

dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/cik.c

5168

dev_info(rdev->dev, "GPU pci config reset\n");

sys/dev/drm/radeon/evergreen.c

3753

dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3755

dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3757

dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3759

dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3761

dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3763

dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3765

dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3767

dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3769

dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3771

dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3774

dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",

sys/dev/drm/radeon/evergreen.c

3886

dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

sys/dev/drm/radeon/evergreen.c

3957

dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/evergreen.c

3971

dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/evergreen.c

3996

dev_info(rdev->dev, "GPU pci config reset\n");

sys/dev/drm/radeon/ni.c

1843

dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

sys/dev/drm/radeon/ni.c

1846

dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",

sys/dev/drm/radeon/ni.c

1848

dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",

sys/dev/drm/radeon/ni.c

1850

dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",

sys/dev/drm/radeon/ni.c

1852

dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

sys/dev/drm/radeon/ni.c

1932

dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/ni.c

1946

dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/r100.c

2578

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/r100.c

2599

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/r100.c

2607

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/r100.c

2617

dev_info(rdev->dev, "GPU reset succeed\n");

sys/dev/drm/radeon/r300.c

418

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/r300.c

437

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/r300.c

449

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/r300.c

458

dev_info(rdev->dev, "GPU reset succeed\n");

sys/dev/drm/radeon/r600.c

1409

dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",

sys/dev/drm/radeon/r600.c

1559

dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",

sys/dev/drm/radeon/r600.c

1561

dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",

sys/dev/drm/radeon/r600.c

1563

dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",

sys/dev/drm/radeon/r600.c

1565

dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",

sys/dev/drm/radeon/r600.c

1567

dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",

sys/dev/drm/radeon/r600.c

1569

dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",

sys/dev/drm/radeon/r600.c

1571

dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",

sys/dev/drm/radeon/r600.c

1573

dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",

sys/dev/drm/radeon/r600.c

1684

dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

sys/dev/drm/radeon/r600.c

1777

dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/r600.c

1791

dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/r600.c

1816

dev_info(rdev->dev, "GPU pci config reset\n");

sys/dev/drm/radeon/radeon_agp.c

248

dev_info(rdev->dev, "GTT: %juM 0x%08jX - 0x%08jX\n",

sys/dev/drm/radeon/radeon_device.c

1866

dev_info(rdev->dev, "Saved %d dwords of commands "

sys/dev/drm/radeon/radeon_device.c

1873

dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");

sys/dev/drm/radeon/radeon_device.c

1937

dev_info(rdev->dev, "GPU reset failed\n");

sys/dev/drm/radeon/radeon_device.c

515

dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");

sys/dev/drm/radeon/radeon_device.c

580

dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",

sys/dev/drm/radeon/radeon_device.c

617

dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",

sys/dev/drm/radeon/radeon_drv.c

403

dev_info(&pdev->dev,

sys/dev/drm/radeon/radeon_drv.c

426

dev_info(&pdev->dev,

sys/dev/drm/radeon/radeon_fence.c

861

dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016lx and cpu addr 0x%p\n",

sys/dev/drm/radeon/radeon_irq_kms.c

221

dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");

sys/dev/drm/radeon/radeon_irq_kms.c

308

dev_info(rdev->dev, "radeon: using MSI.\n");

sys/dev/drm/radeon/rs600.c

463

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/rs600.c

483

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/rs600.c

491

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/rs600.c

499

dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);

sys/dev/drm/radeon/rs600.c

507

dev_info(rdev->dev, "GPU reset succeed\n");

sys/dev/drm/radeon/rv770.c

1628

dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",

sys/dev/drm/radeon/si.c

3850

dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

sys/dev/drm/radeon/si.c

3853

dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",

sys/dev/drm/radeon/si.c

3855

dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

sys/dev/drm/radeon/si.c

3939

dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/si.c

3953

dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

sys/dev/drm/radeon/si.c

4026

dev_info(rdev->dev, "GPU pci config reset\n");