sys/cpu/x86_64/include/specialreg.h

192

#define CPUID_MWAIT_CX_SUBCNT(edx, cstate) \

sys/cpu/x86_64/include/specialreg.h

193

(((edx) >> ((cstate) * 4)) & 0xf)

sys/dev/drm/i915/i915_drv.h

415

int (*compute_pipe_wm)(struct intel_crtc_state *cstate);

sys/dev/drm/i915/i915_drv.h

420

struct intel_crtc_state *cstate);

sys/dev/drm/i915/i915_drv.h

422

struct intel_crtc_state *cstate);

sys/dev/drm/i915/i915_drv.h

424

struct intel_crtc_state *cstate);

sys/dev/drm/i915/intel_display.c

12657

struct intel_crtc_state *cstate;

sys/dev/drm/i915/intel_display.c

12690

cstate = to_intel_crtc_state(new_crtc_state);

sys/dev/drm/i915/intel_display.c

12693

if (updated & cmask || !cstate->base.active)

sys/dev/drm/i915/intel_display.c

12698

&cstate->wm.skl.ddb,

sys/dev/drm/i915/intel_display.c

12703

entries[i] = &cstate->wm.skl.ddb;

sys/dev/drm/i915/intel_display.c

12711

if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,

sys/dev/drm/i915/intel_display.c

15189

struct drm_crtc_state *cstate;

sys/dev/drm/i915/intel_display.c

15244

for_each_new_crtc_in_state(state, crtc, cstate, i) {

sys/dev/drm/i915/intel_display.c

15245

struct intel_crtc_state *cs = to_intel_crtc_state(cstate);

sys/dev/drm/i915/intel_drv.h

2125

struct intel_crtc_state *cstate);

sys/dev/drm/i915/intel_pm.c

1189

static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

2486

static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

2497

if (!intel_wm_plane_visible(cstate, pstate))

sys/dev/drm/i915/intel_pm.c

2502

method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);

sys/dev/drm/i915/intel_pm.c

2507

method2 = ilk_wm_method2(cstate->pixel_rate,

sys/dev/drm/i915/intel_pm.c

2508

cstate->base.adjusted_mode.crtc_htotal,

sys/dev/drm/i915/intel_pm.c

2519

static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

2529

if (!intel_wm_plane_visible(cstate, pstate))

sys/dev/drm/i915/intel_pm.c

2534

method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);

sys/dev/drm/i915/intel_pm.c

2535

method2 = ilk_wm_method2(cstate->pixel_rate,

sys/dev/drm/i915/intel_pm.c

2536

cstate->base.adjusted_mode.crtc_htotal,

sys/dev/drm/i915/intel_pm.c

2546

static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

2555

if (!intel_wm_plane_visible(cstate, pstate))

sys/dev/drm/i915/intel_pm.c

2560

return ilk_wm_method2(cstate->pixel_rate,

sys/dev/drm/i915/intel_pm.c

2561

cstate->base.adjusted_mode.crtc_htotal,

sys/dev/drm/i915/intel_pm.c

2566

static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

2572

if (!intel_wm_plane_visible(cstate, pstate))

sys/dev/drm/i915/intel_pm.c

2747

struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

2765

result->pri_val = ilk_compute_pri_wm(cstate, pristate,

sys/dev/drm/i915/intel_pm.c

2767

result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);

sys/dev/drm/i915/intel_pm.c

2771

result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);

sys/dev/drm/i915/intel_pm.c

2774

result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);

sys/dev/drm/i915/intel_pm.c

2780

hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

2783

to_intel_atomic_state(cstate->base.state);

sys/dev/drm/i915/intel_pm.c

2785

&cstate->base.adjusted_mode;

sys/dev/drm/i915/intel_pm.c

2788

if (!cstate->base.active)

sys/dev/drm/i915/intel_pm.c

3098

static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

3100

struct drm_atomic_state *state = cstate->base.state;

sys/dev/drm/i915/intel_pm.c

3101

struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);

sys/dev/drm/i915/intel_pm.c

3113

pipe_wm = &cstate->wm.ilk.optimal;

sys/dev/drm/i915/intel_pm.c

3115

drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {

sys/dev/drm/i915/intel_pm.c

3126

pipe_wm->pipe_enabled = cstate->base.active;

sys/dev/drm/i915/intel_pm.c

3145

ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,

sys/dev/drm/i915/intel_pm.c

3149

pipe_wm->linetime = hsw_compute_linetime_wm(cstate);

sys/dev/drm/i915/intel_pm.c

3159

ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,

sys/dev/drm/i915/intel_pm.c

3755

struct intel_crtc_state *cstate;

sys/dev/drm/i915/intel_pm.c

3784

cstate = to_intel_crtc_state(crtc->base.state);

sys/dev/drm/i915/intel_pm.c

3791

&cstate->wm.skl.optimal.planes[plane->id];

sys/dev/drm/i915/intel_pm.c

3822

const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

3836

adjusted_mode = &cstate->base.adjusted_mode;

sys/dev/drm/i915/intel_pm.c

3854

const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

3860

struct drm_atomic_state *state = cstate->base.state;

sys/dev/drm/i915/intel_pm.c

3863

struct drm_crtc *for_crtc = cstate->base.crtc;

sys/dev/drm/i915/intel_pm.c

3871

if (WARN_ON(!state) || !cstate->base.active) {

sys/dev/drm/i915/intel_pm.c

3883

ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,

sys/dev/drm/i915/intel_pm.c

4045

skl_plane_downscale_amount(const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4053

if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))

sys/dev/drm/i915/intel_pm.c

4120

struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

4123

struct drm_crtc_state *crtc_state = &cstate->base;

sys/dev/drm/i915/intel_pm.c

4133

if (!cstate->base.enable)

sys/dev/drm/i915/intel_pm.c

4141

if (!intel_wm_plane_visible(cstate,

sys/dev/drm/i915/intel_pm.c

4149

plane_downscale = skl_plane_downscale_amount(cstate,

sys/dev/drm/i915/intel_pm.c

4158

pipe_downscale = skl_pipe_downscale_amount(cstate);

sys/dev/drm/i915/intel_pm.c

4179

skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4218

down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);

sys/dev/drm/i915/intel_pm.c

4233

struct drm_crtc_state *cstate = &intel_cstate->base;

sys/dev/drm/i915/intel_pm.c

4234

struct drm_atomic_state *state = cstate->state;

sys/dev/drm/i915/intel_pm.c

4243

drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {

sys/dev/drm/i915/intel_pm.c

4329

skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,

sys/dev/drm/i915/intel_pm.c

4335

drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {

sys/dev/drm/i915/intel_pm.c

4352

skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4355

struct drm_atomic_state *state = cstate->base.state;

sys/dev/drm/i915/intel_pm.c

4356

struct drm_crtc *crtc = cstate->base.crtc;

sys/dev/drm/i915/intel_pm.c

4360

struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;

sys/dev/drm/i915/intel_pm.c

4378

if (!cstate->base.active) {

sys/dev/drm/i915/intel_pm.c

4383

total_data_rate = skl_get_total_relative_data_rate(cstate,

sys/dev/drm/i915/intel_pm.c

4386

skl_ddb_get_pipe_allocation_limits(dev, cstate, total_data_rate, ddb,

sys/dev/drm/i915/intel_pm.c

4392

skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);

sys/dev/drm/i915/intel_pm.c

4515

intel_get_linetime_us(struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

4521

if (!cstate->base.active)

sys/dev/drm/i915/intel_pm.c

4524

pixel_rate = cstate->pixel_rate;

sys/dev/drm/i915/intel_pm.c

4529

crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;

sys/dev/drm/i915/intel_pm.c

4536

skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4543

if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))

sys/dev/drm/i915/intel_pm.c

4550

adjusted_pixel_rate = cstate->pixel_rate;

sys/dev/drm/i915/intel_pm.c

4551

downscale_amount = skl_plane_downscale_amount(cstate, pstate);

sys/dev/drm/i915/intel_pm.c

4559

struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4568

to_intel_atomic_state(cstate->base.state);

sys/dev/drm/i915/intel_pm.c

4571

if (!intel_wm_plane_visible(cstate, intel_pstate))

sys/dev/drm/i915/intel_pm.c

4604

wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,

sys/dev/drm/i915/intel_pm.c

4660

intel_get_linetime_us(cstate));

sys/dev/drm/i915/intel_pm.c

4666

struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4680

to_intel_atomic_state(cstate->base.state);

sys/dev/drm/i915/intel_pm.c

4685

!intel_wm_plane_visible(cstate, intel_pstate)) {

sys/dev/drm/i915/intel_pm.c

4702

cstate->base.adjusted_mode.crtc_htotal,

sys/dev/drm/i915/intel_pm.c

4709

if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /

sys/dev/drm/i915/intel_pm.c

4817

struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4823

struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);

sys/dev/drm/i915/intel_pm.c

4851

cstate,

sys/dev/drm/i915/intel_pm.c

4869

skl_compute_linetime_wm(struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

4871

struct drm_atomic_state *state = cstate->base.state;

sys/dev/drm/i915/intel_pm.c

4876

linetime_us = intel_get_linetime_us(cstate);

sys/dev/drm/i915/intel_pm.c

4891

static void skl_compute_transition_wm(struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4897

struct drm_device *dev = cstate->base.crtc->dev;

sys/dev/drm/i915/intel_pm.c

4903

if (!cstate->base.active)

sys/dev/drm/i915/intel_pm.c

4946

static int skl_build_pipe_wm(struct intel_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

4950

struct drm_device *dev = cstate->base.crtc->dev;

sys/dev/drm/i915/intel_pm.c

4951

struct drm_crtc_state *crtc_state = &cstate->base;

sys/dev/drm/i915/intel_pm.c

4969

enum i915_pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;

sys/dev/drm/i915/intel_pm.c

4975

ret = skl_compute_plane_wm_params(dev_priv, cstate,

sys/dev/drm/i915/intel_pm.c

4980

ret = skl_compute_wm_levels(dev_priv, ddb, cstate,

sys/dev/drm/i915/intel_pm.c

4985

skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],

sys/dev/drm/i915/intel_pm.c

4993

ret = skl_compute_plane_wm_params(dev_priv, cstate,

sys/dev/drm/i915/intel_pm.c

4999

ret = skl_compute_wm_levels(dev_priv, ddb, cstate,

sys/dev/drm/i915/intel_pm.c

5007

pipe_wm->linetime = skl_compute_linetime_wm(cstate);

sys/dev/drm/i915/intel_pm.c

5131

static int skl_update_pipe_wm(struct drm_crtc_state *cstate,

sys/dev/drm/i915/intel_pm.c

5137

struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);

sys/dev/drm/i915/intel_pm.c

5156

struct drm_crtc_state *cstate;

sys/dev/drm/i915/intel_pm.c

5159

for_each_new_crtc_in_state(state, crtc, cstate, i)

sys/dev/drm/i915/intel_pm.c

5166

skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

5168

struct drm_atomic_state *state = cstate->base.state;

sys/dev/drm/i915/intel_pm.c

5170

struct drm_crtc *crtc = cstate->base.crtc;

sys/dev/drm/i915/intel_pm.c

5180

drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {

sys/dev/drm/i915/intel_pm.c

5204

struct intel_crtc_state *cstate;

sys/dev/drm/i915/intel_pm.c

5209

for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {

sys/dev/drm/i915/intel_pm.c

5210

ret = skl_allocate_pipe_ddb(cstate, ddb);

sys/dev/drm/i915/intel_pm.c

5214

ret = skl_ddb_add_affected_planes(cstate);

sys/dev/drm/i915/intel_pm.c

5230

const struct drm_crtc_state *cstate;

sys/dev/drm/i915/intel_pm.c

5236

for_each_new_crtc_in_state(state, crtc, cstate, i) {

sys/dev/drm/i915/intel_pm.c

5265

const struct drm_crtc_state *cstate;

sys/dev/drm/i915/intel_pm.c

5286

for_each_new_crtc_in_state(state, crtc, cstate, i)

sys/dev/drm/i915/intel_pm.c

5339

struct intel_crtc_state *cstate;

sys/dev/drm/i915/intel_pm.c

5341

cstate = intel_atomic_get_crtc_state(state, intel_crtc);

sys/dev/drm/i915/intel_pm.c

5342

if (IS_ERR(cstate))

sys/dev/drm/i915/intel_pm.c

5343

return PTR_ERR(cstate);

sys/dev/drm/i915/intel_pm.c

5353

struct drm_crtc_state *cstate;

sys/dev/drm/i915/intel_pm.c

5381

for_each_new_crtc_in_state(state, crtc, cstate, i) {

sys/dev/drm/i915/intel_pm.c

5383

to_intel_crtc_state(cstate);

sys/dev/drm/i915/intel_pm.c

5388

ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,

sys/dev/drm/i915/intel_pm.c

5409

struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

5411

struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);

sys/dev/drm/i915/intel_pm.c

5413

struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;

sys/dev/drm/i915/intel_pm.c

5434

struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

5436

struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);

sys/dev/drm/i915/intel_pm.c

5448

if (cstate->base.active_changed)

sys/dev/drm/i915/intel_pm.c

5449

skl_atomic_update_crtc_wm(state, cstate);

sys/dev/drm/i915/intel_pm.c

5511

struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

5513

struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);

sys/dev/drm/i915/intel_pm.c

5514

struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);

sys/dev/drm/i915/intel_pm.c

5517

intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;

sys/dev/drm/i915/intel_pm.c

5523

struct intel_crtc_state *cstate)

sys/dev/drm/i915/intel_pm.c

5525

struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);

sys/dev/drm/i915/intel_pm.c

5526

struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);

sys/dev/drm/i915/intel_pm.c

5529

if (cstate->wm.need_postvbl_update) {

sys/dev/drm/i915/intel_pm.c

5530

intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;

sys/dev/drm/i915/intel_pm.c

5590

struct intel_crtc_state *cstate;

sys/dev/drm/i915/intel_pm.c

5595

cstate = to_intel_crtc_state(crtc->state);

sys/dev/drm/i915/intel_pm.c

5597

skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);

sys/dev/drm/i915/intel_pm.c

5622

struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);

sys/dev/drm/i915/intel_pm.c

5623

struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;

sys/dev/drm/ttm/ttm_page_alloc.c

229

enum ttm_caching_state cstate)

sys/dev/drm/ttm/ttm_page_alloc.c

233

if (cstate == tt_cached)

sys/dev/drm/ttm/ttm_page_alloc.c

236

if (cstate == tt_wc)

sys/dev/drm/ttm/ttm_page_alloc.c

457

enum ttm_caching_state cstate, unsigned cpages)

sys/dev/drm/ttm/ttm_page_alloc.c

461

switch (cstate) {

sys/dev/drm/ttm/ttm_page_alloc.c

484

int ttm_flags, enum ttm_caching_state cstate,

sys/dev/drm/ttm/ttm_page_alloc.c

502

int ttm_flags, enum ttm_caching_state cstate,

sys/dev/drm/ttm/ttm_page_alloc.c

530

cstate, cpages);

sys/dev/drm/ttm/ttm_page_alloc.c

533

ttm_flags, cstate,

sys/dev/drm/ttm/ttm_page_alloc.c

555

cstate, cpages);

sys/dev/drm/ttm/ttm_page_alloc.c

558

ttm_flags, cstate,

sys/dev/drm/ttm/ttm_page_alloc.c

568

r = ttm_set_pages_caching(caching_array, cstate, cpages);

sys/dev/drm/ttm/ttm_page_alloc.c

571

ttm_flags, cstate,

sys/dev/drm/ttm/ttm_page_alloc.c

585

enum ttm_caching_state cstate,

sys/dev/drm/ttm/ttm_page_alloc.c

616

cstate, alloc_size, 0);

sys/dev/drm/ttm/ttm_page_alloc.c

645

enum ttm_caching_state cstate,

sys/dev/drm/ttm/ttm_page_alloc.c

654

ttm_page_pool_fill_locked(pool, ttm_flags, cstate, count,

sys/dev/drm/ttm/ttm_page_alloc.c

678

enum ttm_caching_state cstate)

sys/dev/drm/ttm/ttm_page_alloc.c

680

struct ttm_page_pool *pool = ttm_get_pool(flags, false, cstate);

sys/dev/drm/ttm/ttm_page_alloc.c

728

enum ttm_caching_state cstate)

sys/dev/drm/ttm/ttm_page_alloc.c

730

struct ttm_page_pool *pool = ttm_get_pool(flags, false, cstate);

sys/dev/drm/ttm/ttm_page_alloc.c

765

npages = ttm_page_pool_get_pages(pool, &plist, flags, cstate, npages, 0);

sys/dev/drm/ttm/ttm_page_alloc.c

784

r = ttm_alloc_new_pages(&plist, gfp_flags, flags, cstate, npages, 0);

sys/dev/drm/ttm/ttm_page_alloc.c

792

ttm_put_pages(pages, count, flags, cstate);

sys/dev/drm/ttm/ttm_page_alloc_dma.c

324

static enum pool_type ttm_to_type(int flags, enum ttm_caching_state cstate)

sys/dev/drm/ttm/ttm_page_alloc_dma.c

330

if (cstate == tt_cached)

sys/dev/drm/ttm/ttm_page_alloc_dma.c

332

else if (cstate == tt_uncached)

sys/dev/powermng/powernow/powernow.c

129

k8pnow_states(struct k8pnow_cpu_state *cstate, uint32_t cpusig,

sys/dev/powermng/powernow/powernow.c

132

k8pnow_decode_pst(struct k8pnow_cpu_state *cstate, uint8_t * p);

sys/dev/powermng/powernow/powernow.c

139

k8pnow_decode_pst(struct k8pnow_cpu_state *cstate, uint8_t * p)

sys/dev/powermng/powernow/powernow.c

143

for (n = 0, i = 0; i < cstate->n_states; i++) {

sys/dev/powermng/powernow/powernow.c

153

while (j > 0 && cstate->state_table[j - 1].freq > state.freq) {

sys/dev/powermng/powernow/powernow.c

154

memcpy(&cstate->state_table[j],

sys/dev/powermng/powernow/powernow.c

155

&cstate->state_table[j - 1],

sys/dev/powermng/powernow/powernow.c

159

memcpy(&cstate->state_table[j], &state,

sys/dev/powermng/powernow/powernow.c

167

k8pnow_states(struct k8pnow_cpu_state *cstate, uint32_t cpusig,

sys/dev/powermng/powernow/powernow.c

181

cstate->vst = psb->ttime;

sys/dev/powermng/powernow/powernow.c

182

cstate->rvo = PN8_PSB_TO_RVO(psb->reserved);

sys/dev/powermng/powernow/powernow.c

183

cstate->irt = PN8_PSB_TO_IRT(psb->reserved);

sys/dev/powermng/powernow/powernow.c

184

cstate->mvs = PN8_PSB_TO_MVS(psb->reserved);

sys/dev/powermng/powernow/powernow.c

185

cstate->low = PN8_PSB_TO_BATT(psb->reserved);

sys/dev/powermng/powernow/powernow.c

189

cstate->pll = pst->pll;

sys/dev/powermng/powernow/powernow.c

190

cstate->n_states = pst->n_states;

sys/dev/powermng/powernow/powernow.c

193

return (k8pnow_decode_pst(cstate,

sys/dev/powermng/powernow/powernow.c

197

* cstate->n_states;

sys/dev/powermng/powernow/powernow.c

210

struct k8pnow_cpu_state *cstate;

sys/dev/powermng/powernow/powernow.c

216

cstate = k8pnow_current_state;

sys/dev/powermng/powernow/powernow.c

217

for (i = 0; i < cstate->n_states; i++) {

sys/dev/powermng/powernow/powernow.c

218

if (cstate->state_table[i].fid == cfid &&

sys/dev/powermng/powernow/powernow.c

219

cstate->state_table[i].vid == cvid)

sys/dev/powermng/powernow/powernow.c

220

return (cstate->state_table[i].freq);

sys/dev/powermng/powernow/powernow.c

234

struct k8pnow_cpu_state *cstate;

sys/dev/powermng/powernow/powernow.c

244

cstate = k8pnow_current_state;

sys/dev/powermng/powernow/powernow.c

245

for (i = 0; i < cstate->n_states; i++) {

sys/dev/powermng/powernow/powernow.c

246

if (cstate->state_table[i].freq >= freq) {

sys/dev/powermng/powernow/powernow.c

247

fid = cstate->state_table[i].fid;

sys/dev/powermng/powernow/powernow.c

248

vid = cstate->state_table[i].vid;

sys/dev/powermng/powernow/powernow.c

261

val = cvid - (1 << cstate->mvs);

sys/dev/powermng/powernow/powernow.c

265

COUNT_OFF_VST(cstate->vst);

sys/dev/powermng/powernow/powernow.c

269

for (rvo = cstate->rvo; rvo > 0 && cvid > 0; --rvo) {

sys/dev/powermng/powernow/powernow.c

277

COUNT_OFF_VST(cstate->vst);

sys/dev/powermng/powernow/powernow.c

292

WRITE_FIDVID(val, cvid, (uint64_t) cstate->pll * 1000 / 5);

sys/dev/powermng/powernow/powernow.c

295

COUNT_OFF_IRT(cstate->irt);

sys/dev/powermng/powernow/powernow.c

298

WRITE_FIDVID(fid, cvid, (uint64_t) cstate->pll * 1000 / 5);

sys/dev/powermng/powernow/powernow.c

301

COUNT_OFF_IRT(cstate->irt);

sys/dev/powermng/powernow/powernow.c

308

COUNT_OFF_VST(cstate->vst);

sys/dev/powermng/powernow/powernow.c

311

cpuspeed = cstate->state_table[i].freq;

sys/dev/powermng/powernow/powernow.c

320

struct k8pnow_cpu_state *cstate;

sys/dev/powermng/powernow/powernow.c

322

cstate = k8pnow_current_state;

sys/dev/powermng/powernow/powernow.c

328

for (i = cstate->n_states; i > 0; i--) {

sys/dev/powermng/powernow/powernow.c

329

state = &cstate->state_table[i - 1];

sys/dev/powermng/powernow/powernow.c

351

struct k8pnow_cpu_state *cstate;

sys/dev/powermng/powernow/powernow.c

366

cstate = kmalloc(sizeof(struct k8pnow_cpu_state), M_DEVBUF, M_WAITOK);

sys/dev/powermng/powernow/powernow.c

367

cstate->n_states = 0;

sys/dev/powermng/powernow/powernow.c

377

k8pnow_states(cstate, regs[0], maxfid, maxvid);

sys/dev/powermng/powernow/powernow.c

379

if (cstate->n_states) {

sys/dev/powermng/powernow/powernow.c

380

freq_len = cstate->n_states * (sizeof("9999 ") - 1) + 1;

sys/dev/powermng/powernow/powernow.c

383

for (i = cstate->n_states; i > 0; i--) {

sys/dev/powermng/powernow/powernow.c

384

state = &cstate->state_table[i - 1];

sys/dev/powermng/powernow/powernow.c

391

k8pnow_current_state = cstate;

sys/dev/powermng/powernow/powernow.c

394

kfree(cstate, M_DEVBUF);

sys/net/ppp_layer/slcompress.c

157

struct cstate *cs = comp->last_cs->cs_next;

sys/net/ppp_layer/slcompress.c

201

struct cstate *lcs;

sys/net/ppp_layer/slcompress.c

202

struct cstate *lastcs = comp->last_cs;

sys/net/ppp_layer/slcompress.c

463

struct cstate *cs;

sys/net/ppp_layer/slcompress.c

67

struct cstate *tstate = comp->tstate;

sys/net/slcompress.h

122

struct cstate *cs_next; /* next most recently used cstate (xmit only) */

sys/net/slcompress.h

139

struct cstate *last_cs; /* most recently used tstate */

sys/net/slcompress.h

153

struct cstate tstate[MAX_STATES]; /* xmit connection states */

sys/net/slcompress.h

154

struct cstate rstate[MAX_STATES]; /* receive connection states */

sys/netgraph/vjc/ng_vjc.c

359

struct cstate *const cs = &sl->tstate[i];

sys/netgraph7/vjc/ng_vjc.c

353

struct cstate *const cs = &sl->tstate[i];

usr.sbin/ppp/slcompress.c

147

struct cstate *cs = comp->last_cs->cs_next;

usr.sbin/ppp/slcompress.c

196

struct cstate *lcs;

usr.sbin/ppp/slcompress.c

197

struct cstate *lastcs = comp->last_cs;

usr.sbin/ppp/slcompress.c

420

struct cstate *cs;

usr.sbin/ppp/slcompress.c

71

struct cstate *tstate = comp->tstate;

usr.sbin/ppp/slcompress.h

101

struct cstate *cs_next; /* next most recently used cstate (xmit only) */

usr.sbin/ppp/slcompress.h

119

struct cstate *last_cs; /* most recently used tstate */

usr.sbin/ppp/slcompress.h

123

struct cstate tstate[MAX_VJ_STATES]; /* xmit connection states */

usr.sbin/ppp/slcompress.h

124

struct cstate rstate[MAX_VJ_STATES]; /* receive connection states */