csr_write_4
csr_write_4(sc, SF_CQ_CONSIDX,
csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
csr_write_4(sc, SF_IMR, 0x00000000);
csr_write_4(sc, SF_ISR, status);
csr_write_4(sc, SF_IMR, SF_INTRS);
csr_write_4(sc, i, 0);
csr_write_4(sc, SF_STATS_BASE +
csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
csr_write_4(sc, SF_CQ_CONSIDX, 0);
csr_write_4(sc, SF_CQ_PRODIDX, 0);
csr_write_4(sc, SF_RXCQ_CTL_1,
csr_write_4(sc, SF_RXDQ_ADDR_Q1,
csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
csr_write_4(sc, SF_TXCQ_CTL,
csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
csr_write_4(sc, SF_TXDQ_CTL,
csr_write_4(sc, SF_IMR, SF_INTRS);
csr_write_4(sc, SF_TXDQ_PRODIDX,
csr_write_4(sc, SF_GEN_ETH_CTL, 0);
csr_write_4(sc, SF_CQ_CONSIDX, 0);
csr_write_4(sc, SF_CQ_PRODIDX, 0);
csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
csr_write_4(sc, SF_RXDQ_CTL_1, 0);
csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
csr_write_4(sc, SF_TXCQ_CTL, 0);
csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
csr_write_4(sc, SF_TXDQ_CTL, 0);
csr_write_4(sc, SF_STATS_BASE +
static void csr_write_4 (struct sf_softc *, int, u_int32_t);
csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
csr_write_4(sc, SF_RXFILT_HASH_BASE +
csr_write_4(sc, SF_PHY_REG(phy, reg), val);
csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
csr_write_4(sc, i, 0);
csr_write_4(sc, SF_GEN_ETH_CTL, 0);
csr_write_4(sc, SF_CQ_CONSIDX,
csr_write_4(sc, SF_RXDQ_PTR_Q1,