cmd_tbl
if (!bp->cmd_tbl.transmitter_control)
return bp->cmd_tbl.transmitter_control(bp, cntl);
if (!bp->cmd_tbl.dig_encoder_control)
return bp->cmd_tbl.dig_encoder_control(bp, cntl);
if (!bp->cmd_tbl.adjust_display_pll)
return bp->cmd_tbl.adjust_display_pll(bp, bp_params);
if (!bp->cmd_tbl.set_pixel_clock)
return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
if (!bp->cmd_tbl.set_dce_clock)
return bp->cmd_tbl.set_dce_clock(bp, bp_params);
if (!bp->cmd_tbl.enable_spread_spectrum_on_ppll)
return bp->cmd_tbl.enable_spread_spectrum_on_ppll(
if (!bp->cmd_tbl.set_crtc_timing)
return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
if (!bp->cmd_tbl.program_clock)
return bp->cmd_tbl.program_clock(bp, bp_params);
if (!bp->cmd_tbl.enable_crtc)
return bp->cmd_tbl.enable_crtc(bp, id, enable);
if (!bp->cmd_tbl.select_crtc_source)
return bp->cmd_tbl.select_crtc_source(bp, bp_params);
if (!bp->cmd_tbl.enable_disp_power_gating)
return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
if (!bp->cmd_tbl.transmitter_control)
return bp->cmd_tbl.transmitter_control(bp, cntl);
if (!bp->cmd_tbl.dig_encoder_control)
return bp->cmd_tbl.dig_encoder_control(bp, cntl);
if (!bp->cmd_tbl.set_pixel_clock)
return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
if (!bp->cmd_tbl.set_dce_clock)
return bp->cmd_tbl.set_dce_clock(bp, bp_params);
if (!bp->cmd_tbl.set_crtc_timing)
return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
if (!bp->cmd_tbl.enable_crtc)
return bp->cmd_tbl.enable_crtc(bp, id, enable);
if (!bp->cmd_tbl.select_crtc_source)
return bp->cmd_tbl.select_crtc_source(bp, bp_params);
if (!bp->cmd_tbl.enable_disp_power_gating)
return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
if (bp->cmd_tbl.get_smu_clock_info != NULL) {
bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
if (bp->cmd_tbl.get_smu_clock_info != NULL) {
bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
struct cmd_tbl cmd_tbl;
struct cmd_tbl cmd_tbl;
bp->cmd_tbl.enable_spread_spectrum_on_ppll =
bp->cmd_tbl.enable_spread_spectrum_on_ppll =
bp->cmd_tbl.enable_spread_spectrum_on_ppll =
bp->cmd_tbl.enable_spread_spectrum_on_ppll = NULL;
bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v3;
bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v4;
bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v5;
bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v2;
bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v3;
bp->cmd_tbl.adjust_display_pll = NULL;
struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
bp->cmd_tbl.dac1_encoder_control = dac1_encoder_control_v1;
bp->cmd_tbl.dac1_encoder_control = NULL;
bp->cmd_tbl.dac2_encoder_control = dac2_encoder_control_v1;
bp->cmd_tbl.dac2_encoder_control = NULL;
cmd_tbl->encoder_control_dig1 = encoder_control_dig1_v1;
cmd_tbl->encoder_control_dig1 = NULL;
cmd_tbl->encoder_control_dig2 = encoder_control_dig2_v1;
bp->cmd_tbl.dac1_output_control = dac1_output_control_v1;
cmd_tbl->encoder_control_dig2 = NULL;
bp->cmd_tbl.dac1_output_control = NULL;
bp->cmd_tbl.dac2_output_control = dac2_output_control_v1;
bp->cmd_tbl.dac2_output_control = NULL;
cmd_tbl->dig_encoder_control = encoder_control_dig_v1;
bp->cmd_tbl.set_crtc_timing =
bp->cmd_tbl.set_crtc_timing = NULL;
bp->cmd_tbl.set_crtc_timing = set_crtc_timing_v1;
bp->cmd_tbl.set_crtc_timing = NULL;
struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
if (cmd_tbl->encoder_control_dig1 != NULL)
cmd_tbl->encoder_control_dig1(bp, cntl);
if (cmd_tbl->encoder_control_dig2 != NULL)
cmd_tbl->encoder_control_dig2(bp, cntl);
bp->cmd_tbl.select_crtc_source = select_crtc_source_v2;
bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
bp->cmd_tbl.select_crtc_source = NULL;
bp->cmd_tbl.enable_crtc = enable_crtc_v1;
bp->cmd_tbl.enable_crtc = NULL;
bp->cmd_tbl.enable_crtc_mem_req = enable_crtc_mem_req_v1;
bp->cmd_tbl.enable_crtc_mem_req = NULL;
bp->cmd_tbl.program_clock = program_clock_v5;
bp->cmd_tbl.program_clock = program_clock_v6;
bp->cmd_tbl.program_clock = NULL;
bp->cmd_tbl.external_encoder_control =
bp->cmd_tbl.external_encoder_control = NULL;
bp->cmd_tbl.enable_disp_power_gating =
bp->cmd_tbl.enable_disp_power_gating = NULL;
bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
bp->cmd_tbl.set_dce_clock = NULL;
bp->cmd_tbl.transmitter_control = transmitter_control_v2;
bp->cmd_tbl.transmitter_control = transmitter_control_v3;
bp->cmd_tbl.transmitter_control = transmitter_control_v4;
bp->cmd_tbl.transmitter_control = transmitter_control_v1_5;
bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
bp->cmd_tbl.transmitter_control = NULL;
bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v3;
bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v5;
bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v6;
bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
bp->cmd_tbl.set_pixel_clock = NULL;
bp->cmd_tbl.dig_encoder_control = NULL;
bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
bp->cmd_tbl.transmitter_control = NULL;
bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
bp->cmd_tbl.set_pixel_clock = NULL;
bp->cmd_tbl.set_crtc_timing =
bp->cmd_tbl.set_crtc_timing = NULL;
bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
bp->cmd_tbl.select_crtc_source = NULL;
bp->cmd_tbl.enable_crtc = enable_crtc_v1;
bp->cmd_tbl.enable_crtc = NULL;
bp->cmd_tbl.external_encoder_control =
bp->cmd_tbl.external_encoder_control = NULL;
bp->cmd_tbl.enable_disp_power_gating =
bp->cmd_tbl.enable_disp_power_gating = NULL;
bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
bp->cmd_tbl.set_dce_clock = NULL;
bp->cmd_tbl.get_smu_clock_info = get_smu_clock_info_v3_1;
bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5;