sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

330

static const struct dce110_clk_src_regs clk_src_regs[] = {

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

331

clk_src_regs(0),

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

332

clk_src_regs(1),

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

333

clk_src_regs(2)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

890

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

892

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

894

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

899

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

902

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

904

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1243

&clk_src_regs[0], false);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1246

&clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

357

static const struct dce110_clk_src_regs clk_src_regs[] = {

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

358

clk_src_regs(0),

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

359

clk_src_regs(1),

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

360

clk_src_regs(2)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1172

&clk_src_regs[0], false);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1177

&clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1182

&clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1187

&clk_src_regs[3], false);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1192

&clk_src_regs[4], false);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1197

&clk_src_regs[5], false);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1202

CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

364

static const struct dce110_clk_src_regs clk_src_regs[] = {

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

365

clk_src_regs(0, A),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

366

clk_src_regs(1, B),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

367

clk_src_regs(2, C),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

368

clk_src_regs(3, D),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

369

clk_src_regs(4, E),

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

370

clk_src_regs(5, F)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

349

static const struct dce110_clk_src_regs clk_src_regs[] = {

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

350

clk_src_regs(0, A),

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

351

clk_src_regs(1, B),

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

352

clk_src_regs(2, C),

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

353

clk_src_regs(3, D),

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

354

clk_src_regs(4, E),

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

355

clk_src_regs(5, F)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

946

&clk_src_regs[0], false);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

950

&clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

954

&clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

958

&clk_src_regs[3], false);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

962

&clk_src_regs[4], false);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

966

&clk_src_regs[5], false);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

972

&clk_src_regs[0], true);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1109

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1111

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1113

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1118

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1121

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1123

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1319

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1321

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1326

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1329

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

349

static const struct dce110_clk_src_regs clk_src_regs[] = {

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

350

clk_src_regs(0),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

351

clk_src_regs(1),

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

352

clk_src_regs(2)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

899

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

901

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

903

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

908

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

911

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

913

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1240

&clk_src_regs[0], false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1244

&clk_src_regs[1], false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1248

&clk_src_regs[2], false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1255

&clk_src_regs[3], false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1261

&clk_src_regs[3], false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1275

&clk_src_regs[0], true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

484

static const struct dce110_clk_src_regs clk_src_regs[] = {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

485

clk_src_regs(0, A),

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

486

clk_src_regs(1, B),

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

487

clk_src_regs(2, C),

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

488

clk_src_regs(3, D)