sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1002

data->scatter_gather_page_width[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1003

data->scatter_gather_page_height[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1006

data->scatter_gather_page_width[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1007

data->scatter_gather_page_height[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1010

data->scatter_gather_page_width[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1011

data->scatter_gather_page_height[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1014

data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1018

data->useful_pte_per_pte_request = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1021

data->scatter_gather_page_width[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1022

data->scatter_gather_page_height[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1025

data->scatter_gather_page_width[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1026

data->scatter_gather_page_height[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1029

data->scatter_gather_page_width[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1030

data->scatter_gather_page_height[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1033

data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1036

data->pte_request_per_chunk[i] = bw_div(bw_div(bw_int_to_fixed(dceip->chunk_width), data->scatter_gather_page_width[i]), data->useful_pte_per_pte_request);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1037

data->scatter_gather_pte_requests_in_row[i] = bw_div(bw_mul(bw_ceil2(bw_mul(bw_div(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(dceip->chunk_width)), data->pte_request_per_chunk[i]), bw_int_to_fixed(1)), data->scatter_gather_row_height), data->scatter_gather_page_height[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1039

if (bw_equ(data->peak_pte_request_to_eviction_ratio_limiting, bw_int_to_fixed(0))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1043

data->scatter_gather_pte_request_limit[i] = bw_max2(dceip->minimum_outstanding_pte_request_limit, bw_min2(data->scatter_gather_pte_requests_in_vblank, bw_ceil2(bw_mul(bw_mul(bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->memory_chunk_size_in_bytes[i]), data->pte_request_per_chunk[i]), data->peak_pte_request_to_eviction_ratio_limiting), bw_int_to_fixed(1))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1050

data->inefficient_linear_pitch_in_bytes = bw_mul(bw_mul(bw_int_to_fixed(256), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1071

data->cursor_total_data = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1072

data->cursor_total_request_groups = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1073

data->scatter_gather_total_pte_requests = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1074

data->scatter_gather_total_pte_request_groups = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1077

data->cursor_total_data = bw_add(data->cursor_total_data, bw_mul(bw_mul(bw_int_to_fixed(2), data->cursor_width_pixels[i]), bw_int_to_fixed(4)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1079

data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_int_to_fixed((dceip->cursor_max_outstanding_group_num + 1)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1082

data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_ceil2(bw_div(data->cursor_width_pixels[i], dceip->cursor_chunk_width), bw_int_to_fixed(1)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1086

data->scatter_gather_total_pte_request_groups = bw_add(data->scatter_gather_total_pte_request_groups, bw_ceil2(bw_div(data->scatter_gather_pte_request_limit[i], bw_ceil2(data->pte_request_per_chunk[i], bw_int_to_fixed(1))), bw_int_to_fixed(1)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1090

data->tile_width_in_pixels = bw_int_to_fixed(8);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1091

data->dmif_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1092

data->mcifwr_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1096

data->bytes_per_page_close_open = bw_mul(data->lines_interleaved_in_mem_access[i], bw_max2(bw_mul(bw_mul(bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->tile_width_in_pixels), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels)), bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->scatter_gather_page_width[i])));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1098

else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1112

data->dmif_total_page_close_open_time = bw_div(bw_mul((bw_add(bw_add(data->dmif_total_number_of_data_request_page_close_open, data->scatter_gather_total_pte_request_groups), data->cursor_total_request_groups)), vbios->trc), bw_int_to_fixed(1000));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1113

data->mcifwr_total_page_close_open_time = bw_div(bw_mul(data->mcifwr_total_number_of_data_request_page_close_open, vbios->trc), bw_int_to_fixed(1000));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1119

data->total_requests_for_adjusted_dmif_size = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1127

data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed(vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1129

data->total_display_reads_required_data = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1130

data->total_display_reads_required_dram_access_data = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1131

data->total_display_writes_required_data = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1132

data->total_display_writes_required_dram_access_data = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1151

data->display_reads_required_dram_access_data = bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed((8 * vbios->dram_channel_width_in_bits / 8)), data->bytes_per_request[i]), bw_int_to_fixed(1)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1158

data->total_display_writes_required_dram_access_data = bw_add(data->total_display_writes_required_dram_access_data, bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits), data->bytes_per_request[i]), bw_int_to_fixed(1))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1162

data->total_display_reads_required_data = bw_add(bw_add(data->total_display_reads_required_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1163

data->total_display_reads_required_dram_access_data = bw_add(bw_add(data->total_display_reads_required_dram_access_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1166

if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(4))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1167

data->src_pixels_for_first_output_pixel[i] = bw_mul(bw_int_to_fixed(4), data->source_width_rounded_up_to_chunks[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1170

if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(2))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1171

data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(512);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1174

data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1177

data->src_data_for_first_output_pixel[i] = bw_div(bw_mul(bw_mul(data->src_pixels_for_first_output_pixel[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1178

data->src_pixels_for_last_output_pixel[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_mul(bw_ceil2(data->vsr[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->horizontal_blank_and_chunk_granularity_factor[i])));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1179

data->src_data_for_last_output_pixel[i] = bw_div(bw_mul(bw_mul(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->lines_interleaved_in_mem_access[i])), bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1185

data->dmif_burst_time[i][j] = bw_max3(data->dmif_total_page_close_open_time, bw_div(data->total_display_reads_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))), bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100)))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1187

data->mcifwr_burst_time[i][j] = bw_max3(data->mcifwr_total_page_close_open_time, bw_div(data->total_display_writes_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_wrchannels)))), bw_div(data->total_display_writes_required_data, (bw_mul(sclk[j], vbios->data_return_bus_width))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1199

data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_add(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->dmif_buffer_transfer_time[i]), data->active_time[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1236

data->v_scaler_efficiency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1240

if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1244

data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1246

data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1249

data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1255

data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1284

if ((bw_equ(dceip->stutter_and_dram_clock_state_change_gated_before_cursor, bw_int_to_fixed(0)) && bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0)))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1285

if (bw_ltn(data->vsr[i], bw_int_to_fixed(2))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1286

data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(1))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1289

data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(3))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1293

data->cursor_latency_hiding[i] = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1299

if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixed(2)) && data->lb_bpc[i] == 8)) && surface_type[i] == bw_def_graphics) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1301

data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(2)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1303

data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(1)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1306

data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_int_to_fixed(1 + data->line_buffer_prefetch[i]), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1313

data->blackout_duration_margin[i][j] = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1314

data->dispclk_required_for_blackout_duration[i][j] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1315

data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1317

if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1321

if (bw_leq(vbios->maximum_blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1322

data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1324

else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1325

data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, bw_sub(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1331

if (bw_ltn(vbios->maximum_blackout_recovery_time, bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1332

data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1334

else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1335

data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, (bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1342

if (bw_mtn(data->blackout_duration_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[high][s_high], vbios->high_voltage_max_dispclk)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1376

data->min_dram_speed_change_margin[i][j] = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1377

data->dram_speed_change_margin = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1378

data->dispclk_required_for_dram_speed_change[i][j] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1384

if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1398

if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1423

data->min_vblank_dram_speed_change_margin = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1427

data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1431

data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1437

data->displays_with_same_mode[i] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1438

if (data->enable[i] == 1 && data->display_pstate_change_enable[i] == 0 && bw_mtn(data->v_blank_dram_speed_change_margin[i], bw_int_to_fixed(0))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1441

data->displays_with_same_mode[i] = bw_add(data->displays_with_same_mode[i], bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1449

number_of_aligned_displays_with_no_margin = bw_fixed_to_int(bw_max2(bw_int_to_fixed(number_of_aligned_displays_with_no_margin), data->displays_with_same_mode[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1455

if (number_of_displays_enabled_with_margin > 0 && (number_of_displays_enabled_with_margin + number_of_aligned_displays_with_no_margin) == number_of_displays_enabled && bw_mtn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(9999)) && bw_ltn(data->dispclk_required_for_dram_speed_change[high][s_high], vbios->high_voltage_max_dispclk)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1474

data->average_bandwidth_no_compression[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(data->bytes_per_pixel[i])), (bw_div(data->h_total[i], data->pixel_rate[i]))), data->vsr[i]), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1478

data->total_average_bandwidth_no_compression = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1479

data->total_average_bandwidth = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1491

data->min_cursor_memory_interface_buffer_size_in_time = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1496

if (bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1498

if (bw_leq(data->cursor_width_pixels[i], bw_int_to_fixed(64)) && dceip->large_cursor == 1) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1504

data->min_cursor_memory_interface_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, bw_div(bw_mul(bw_div(bw_int_to_fixed(num_cursor_lines), data->vsr[i]), data->h_total[i]), data->pixel_rate[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1513

data->chunk_request_delay = bw_fixed_to_int(bw_div(bw_int_to_fixed(512), vbios->high_voltage_max_dispclk));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1516

data->display_reads_time_for_data_transfer = bw_sub(bw_sub(data->min_read_buffer_size_in_time, data->total_dmifmc_urgent_latency), bw_int_to_fixed(data->chunk_request_delay));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1523

data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1526

data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1529

data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1532

data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1535

data->required_dram_bandwidth_gbyte_per_second = bw_div(bw_max2(data->dmif_required_dram_bandwidth, data->mcifwr_required_dram_bandwidth), bw_int_to_fixed(1000));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1536

if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[low]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1537

&& bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[low][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[low][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[low][s_high] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1540

data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1542

else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[mid]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1543

&& bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[mid][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[mid][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[mid][s_high] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1546

data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1548

else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[high]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1549

&& bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1552

data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1557

data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1568

data->required_sclk = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1573

data->required_sclk = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1580

&& bw_ltn(data->required_sclk, sclk[s_low]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_low], vbios->low_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_low] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1586

&& bw_ltn(data->required_sclk, sclk[s_mid1]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid1], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid1] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1592

&& bw_ltn(data->required_sclk, sclk[s_mid2]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid2], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid2] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1598

&& bw_ltn(data->required_sclk, sclk[s_mid3]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid3], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid3] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1604

&& bw_ltn(data->required_sclk, sclk[s_mid4]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid4], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid4] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1610

&& bw_ltn(data->required_sclk, sclk[s_mid5]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid5], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid5] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1616

&& bw_ltn(data->required_sclk, sclk[s_mid6]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid6] == number_of_displays_enabled_with_margin))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1653

data->downspread_factor = bw_add(bw_int_to_fixed(1), bw_div(vbios->down_spread_percentage, bw_int_to_fixed(100)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1691

if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1695

data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1702

data->total_dispclk_required_with_ramping = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1703

data->total_dispclk_required_without_ramping = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1714

data->total_read_request_bandwidth = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1715

data->total_write_request_bandwidth = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1761

else if (bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) && sclk_message == bw_def_low && bw_ltn(data->dispclk, vbios->low_voltage_max_dispclk)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1764

else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid) && bw_ltn(data->dispclk, vbios->mid_voltage_max_dispclk)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1767

else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->high_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid || sclk_message == bw_def_high) && bw_leq(data->dispclk, vbios->high_voltage_max_dispclk)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1788

data->blackout_recovery_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1790

if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1792

data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1793

if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])))))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1794

data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1798

data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1799

if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1800

data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1814

data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1817

data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(64), bw_int_to_fixed(data->bytes_per_pixel[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1820

data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1823

data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(16), bw_int_to_fixed(data->bytes_per_pixel[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1827

data->min_pixels_per_data_fifo_entry = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1842

data->chunk_request_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1843

data->cursor_request_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1847

data->chunk_request_time = bw_add(data->chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * data->bytes_per_pixel[i]), data->useful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(2))))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1851

data->cursor_request_time = (bw_div(data->cursor_total_data, (bw_mul(bw_int_to_fixed(32), sclk[data->sclk_level]))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1865

data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1870

data->stutter_exit_watermark[i] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1871

data->stutter_entry_watermark[i] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1877

data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1910

data->dmifdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_reads_required_dram_access_data, data->dram_bandwidth), data->dmif_total_page_close_open_time), bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1911

if (bw_mtn(data->total_display_writes_required_dram_access_data, bw_int_to_fixed(0))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1912

data->mcifwrdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_writes_required_dram_access_data, data->dram_bandwidth), data->mcifwr_total_page_close_open_time), bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1915

data->mcifwrdram_access_efficiency = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1926

data->stutter_refresh_duration[i] = bw_sub(bw_mul(bw_div(bw_div(bw_mul(bw_div(bw_div(data->adjusted_data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]), bw_max2(bw_int_to_fixed(0), bw_sub(data->stutter_exit_watermark[i], bw_div(bw_mul((bw_sub(data->lb_partitions[i], bw_int_to_fixed(1))), data->h_total[i]), data->pixel_rate[i]))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1927

data->stutter_dmif_buffer_size[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(bw_mul(data->stutter_refresh_duration[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1930

data->min_stutter_refresh_duration = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1938

data->total_bytes_requested = bw_fixed_to_int(bw_add(bw_int_to_fixed(data->total_bytes_requested), (bw_mul(bw_mul(data->source_height_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[i]), bw_int_to_fixed(data->bytes_per_pixel[i])))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1941

data->total_stutter_dmif_buffer_size = bw_fixed_to_int(bw_add(data->stutter_dmif_buffer_size[i], bw_int_to_fixed(data->total_stutter_dmif_buffer_size)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1944

data->stutter_burst_time = bw_div(bw_int_to_fixed(data->total_stutter_dmif_buffer_size), bw_mul(sclk[data->sclk_level], vbios->data_return_bus_width));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1949

data->stutter_efficiency = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1951

else if (bw_ltn(data->time_in_self_refresh, bw_int_to_fixed(0))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1952

data->stutter_efficiency = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1956

data->stutter_efficiency = bw_max2(bw_int_to_fixed(0), bw_mul((bw_sub(bw_int_to_fixed(1), (bw_div(bw_mul((bw_add(vbios->stutter_self_refresh_exit_latency, data->stutter_burst_time)), bw_int_to_fixed(data->num_stutter_bursts)), bw_frc_to_fixed(166666667, 10000))))), bw_int_to_fixed(100)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1961

data->worst_number_of_trips_to_memory = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1964

data->number_of_trips_to_memory_for_getting_apte_row[i] = bw_ceil2(bw_div(data->scatter_gather_pte_requests_in_row[i], data->scatter_gather_pte_request_limit[i]), bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1978

data->latency_for_non_mcifwr_clients = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1984

data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1985

data->nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1989

data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_min2(data->v_blank_nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[i], bw_sub(bw_div(data->src_height[i], data->v_scale_ratio[i]), bw_int_to_fixed(4)))), data->h_total[i]), data->pixel_rate[i]), data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1994

data->display_reads_time_for_data_transfer_and_urgent_latency = bw_sub(data->min_read_buffer_size_in_time, bw_mul(data->total_dmifmc_urgent_trips, bw_int_to_fixed(i)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1999

data->dmif_required_sclk_for_urgent_latency[i] = bw_int_to_fixed(bw_def_na);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2009

data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2010

if (bw_meq(data->max_phyclk, bw_int_to_fixed(270))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2011

data->output_bppdp4_lane_hbr[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(270), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2013

if (bw_meq(data->max_phyclk, bw_int_to_fixed(540))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2014

data->output_bppdp4_lane_hbr2[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(540), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2016

if (bw_meq(data->max_phyclk, bw_int_to_fixed(810))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2017

data->output_bppdp4_lane_hbr3[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(810), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2043

vbios.high_yclk = bw_int_to_fixed(1600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2044

vbios.mid_yclk = bw_int_to_fixed(1600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2046

vbios.low_sclk = bw_int_to_fixed(200);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2047

vbios.mid1_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2048

vbios.mid2_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2049

vbios.mid3_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2050

vbios.mid4_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2051

vbios.mid5_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2052

vbios.mid6_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2054

vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2055

vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2056

vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2057

vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2058

vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2059

vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2060

vbios.data_return_bus_width = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2061

vbios.trc = bw_int_to_fixed(50);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2062

vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2064

vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2066

vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2072

vbios.blackout_duration = bw_int_to_fixed(0); /* us */

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2073

vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2079

dceip.dmif_request_buffer_size = bw_int_to_fixed(768);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2096

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2104

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2105

dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2112

dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2113

dceip.lb_size_per_component444 = bw_int_to_fixed(82176);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2116

bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2117

dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2120

bw_int_to_fixed(164352);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2121

dceip.underlay422_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2123

dceip.cursor_chunk_width = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2124

dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2126

bw_int_to_fixed(1920);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2128

bw_int_to_fixed(1080);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2132

bw_int_to_fixed(25);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2133

dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2136

bw_int_to_fixed(128);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2139

bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2145

dceip.dispclk_per_request = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2149

dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2159

vbios.high_yclk = bw_int_to_fixed(6000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2160

vbios.mid_yclk = bw_int_to_fixed(3200);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2161

vbios.low_yclk = bw_int_to_fixed(1000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2162

vbios.low_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2163

vbios.mid1_sclk = bw_int_to_fixed(400);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2164

vbios.mid2_sclk = bw_int_to_fixed(500);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2165

vbios.mid3_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2166

vbios.mid4_sclk = bw_int_to_fixed(700);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2167

vbios.mid5_sclk = bw_int_to_fixed(800);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2168

vbios.mid6_sclk = bw_int_to_fixed(974);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2169

vbios.high_sclk = bw_int_to_fixed(1154);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2170

vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2171

vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2172

vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2173

vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2174

vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2175

vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2176

vbios.data_return_bus_width = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2177

vbios.trc = bw_int_to_fixed(48);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2178

vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2179

vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2180

vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2181

vbios.nbp_state_change_latency = bw_int_to_fixed(45);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2182

vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2188

vbios.blackout_duration = bw_int_to_fixed(0); /* us */

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2189

vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2195

dceip.dmif_request_buffer_size = bw_int_to_fixed(768);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2212

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2220

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2221

dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2228

dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2229

dceip.lb_size_per_component444 = bw_int_to_fixed(245952);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2232

bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2233

dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2236

bw_int_to_fixed(164352);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2237

dceip.underlay422_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2239

dceip.cursor_chunk_width = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2240

dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2242

bw_int_to_fixed(1920);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2244

bw_int_to_fixed(1080);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2248

bw_int_to_fixed(25);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2249

dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2252

bw_int_to_fixed(128);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2255

bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2261

dceip.dispclk_per_request = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2265

dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2272

vbios.high_yclk = bw_int_to_fixed(6000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2273

vbios.mid_yclk = bw_int_to_fixed(3200);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2274

vbios.low_yclk = bw_int_to_fixed(1000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2275

vbios.low_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2276

vbios.mid1_sclk = bw_int_to_fixed(400);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2277

vbios.mid2_sclk = bw_int_to_fixed(500);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2278

vbios.mid3_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2279

vbios.mid4_sclk = bw_int_to_fixed(700);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2280

vbios.mid5_sclk = bw_int_to_fixed(800);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2281

vbios.mid6_sclk = bw_int_to_fixed(974);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2282

vbios.high_sclk = bw_int_to_fixed(1154);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2283

vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2284

vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2285

vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2286

vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2287

vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2288

vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2289

vbios.data_return_bus_width = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2290

vbios.trc = bw_int_to_fixed(48);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2292

vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2294

vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2295

vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2296

vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2297

vbios.nbp_state_change_latency = bw_int_to_fixed(45);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2298

vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2304

vbios.blackout_duration = bw_int_to_fixed(0); /* us */

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2305

vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2311

dceip.dmif_request_buffer_size = bw_int_to_fixed(768);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2328

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2336

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2337

dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2344

dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2345

dceip.lb_size_per_component444 = bw_int_to_fixed(245952);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2348

bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2349

dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2352

bw_int_to_fixed(164352);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2353

dceip.underlay422_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2355

dceip.cursor_chunk_width = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2356

dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2358

bw_int_to_fixed(1920);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2360

bw_int_to_fixed(1080);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2364

bw_int_to_fixed(25);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2365

dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2368

bw_int_to_fixed(128);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2371

bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2377

dceip.dispclk_per_request = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2381

dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2388

vbios.high_yclk = bw_int_to_fixed(6000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2389

vbios.mid_yclk = bw_int_to_fixed(3200);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2390

vbios.low_yclk = bw_int_to_fixed(1000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2391

vbios.low_sclk = bw_int_to_fixed(678);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2392

vbios.mid1_sclk = bw_int_to_fixed(864);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2393

vbios.mid2_sclk = bw_int_to_fixed(900);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2394

vbios.mid3_sclk = bw_int_to_fixed(920);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2395

vbios.mid4_sclk = bw_int_to_fixed(940);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2396

vbios.mid5_sclk = bw_int_to_fixed(960);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2397

vbios.mid6_sclk = bw_int_to_fixed(980);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2398

vbios.high_sclk = bw_int_to_fixed(1049);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2399

vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2400

vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2401

vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2402

vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2403

vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2404

vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2405

vbios.data_return_bus_width = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2406

vbios.trc = bw_int_to_fixed(48);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2408

vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2410

vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2411

vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2412

vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2413

vbios.nbp_state_change_latency = bw_int_to_fixed(250);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2414

vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2420

vbios.blackout_duration = bw_int_to_fixed(0); /* us */

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2421

vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2427

dceip.dmif_request_buffer_size = bw_int_to_fixed(768);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2444

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2452

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2453

dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2460

dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2461

dceip.lb_size_per_component444 = bw_int_to_fixed(245952);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2464

bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2465

dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2468

bw_int_to_fixed(164352);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2469

dceip.underlay422_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2471

dceip.cursor_chunk_width = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2472

dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2474

bw_int_to_fixed(1920);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2476

bw_int_to_fixed(1080);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2480

bw_int_to_fixed(25);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2481

dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2484

bw_int_to_fixed(128);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2487

bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2493

dceip.dispclk_per_request = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2497

dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2504

vbios.high_yclk = bw_int_to_fixed(1866);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2505

vbios.mid_yclk = bw_int_to_fixed(1866);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2506

vbios.low_yclk = bw_int_to_fixed(1333);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2507

vbios.low_sclk = bw_int_to_fixed(200);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2508

vbios.mid1_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2509

vbios.mid2_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2510

vbios.mid3_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2511

vbios.mid4_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2512

vbios.mid5_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2513

vbios.mid6_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2514

vbios.high_sclk = bw_int_to_fixed(800);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2515

vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2516

vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2517

vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2518

vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2519

vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2520

vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2521

vbios.data_return_bus_width = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2522

vbios.trc = bw_int_to_fixed(50);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2523

vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2525

vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2527

vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2533

vbios.blackout_duration = bw_int_to_fixed(0); /* us */

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2534

vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2540

dceip.dmif_request_buffer_size = bw_int_to_fixed(768);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2557

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2565

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2566

dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2573

dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2574

dceip.lb_size_per_component444 = bw_int_to_fixed(82176);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2577

bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2578

dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2581

bw_int_to_fixed(164352);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2582

dceip.underlay422_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2584

dceip.cursor_chunk_width = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2585

dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2587

bw_int_to_fixed(1920);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2589

bw_int_to_fixed(1080);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2593

bw_int_to_fixed(25);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2594

dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2597

bw_int_to_fixed(128);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2600

bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2606

dceip.dispclk_per_request = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2610

dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2617

vbios.high_yclk = bw_int_to_fixed(2400);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2618

vbios.mid_yclk = bw_int_to_fixed(1700);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2619

vbios.low_yclk = bw_int_to_fixed(1000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2620

vbios.low_sclk = bw_int_to_fixed(300);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2621

vbios.mid1_sclk = bw_int_to_fixed(350);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2622

vbios.mid2_sclk = bw_int_to_fixed(400);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2623

vbios.mid3_sclk = bw_int_to_fixed(500);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2624

vbios.mid4_sclk = bw_int_to_fixed(600);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2625

vbios.mid5_sclk = bw_int_to_fixed(700);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2626

vbios.mid6_sclk = bw_int_to_fixed(760);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2627

vbios.high_sclk = bw_int_to_fixed(776);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2628

vbios.low_voltage_max_dispclk = bw_int_to_fixed(460);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2629

vbios.mid_voltage_max_dispclk = bw_int_to_fixed(670);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2630

vbios.high_voltage_max_dispclk = bw_int_to_fixed(1133);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2631

vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2632

vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2633

vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2634

vbios.data_return_bus_width = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2635

vbios.trc = bw_int_to_fixed(48);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2636

vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2639

vbios.nbp_state_change_latency = bw_int_to_fixed(39);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2640

vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2646

vbios.blackout_duration = bw_int_to_fixed(0); /* us */

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2647

vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2653

dceip.dmif_request_buffer_size = bw_int_to_fixed(2304);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2670

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2678

bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2679

dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2686

dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2687

dceip.lb_size_per_component444 = bw_int_to_fixed(245952);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2690

bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2691

dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2694

bw_int_to_fixed(164352);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2695

dceip.underlay422_lb_size_per_component = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2697

dceip.cursor_chunk_width = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2698

dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2700

bw_int_to_fixed(1920);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2702

bw_int_to_fixed(1080);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2706

bw_int_to_fixed(25);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2707

dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2710

bw_int_to_fixed(128);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2713

bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2719

dceip.dispclk_per_request = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2723

dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

273

data->compression_rate[0] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

274

data->compression_rate[1] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

275

data->compression_rate[2] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

276

data->compression_rate[3] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2793

data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2794

data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2796

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2798

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2799

data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2800

data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2805

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2808

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

281

data->cursor_width_pixels[0] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2811

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2814

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

282

data->cursor_width_pixels[1] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

283

data->cursor_width_pixels[2] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

284

data->cursor_width_pixels[3] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2850

data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2851

data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2852

data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2854

data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2855

data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2862

data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2865

data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(90);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2868

data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(180);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2871

data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(270);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2891

data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2892

data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2898

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2900

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2901

data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2902

data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2907

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2910

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2913

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2916

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2949

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2951

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2952

data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2953

data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2956

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2959

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2961

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2962

data->h_taps[num_displays + 4] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2963

data->v_taps[num_displays + 4] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2964

data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2965

data->v_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2966

data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3036

bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3041

bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3044

bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3047

bw_mul(low_yclk, bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3050

bw_mul(mid_yclk, bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3053

bw_mul(high_yclk, bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3059

nbp_state_change_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3062

nbp_state_change_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3065

nbp_state_change_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3070

nbp_state_change_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3073

nbp_state_change_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3077

nbp_state_change_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3080

nbp_state_change_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3084

nbp_state_change_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3090

stutter_exit_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3093

stutter_exit_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3096

stutter_exit_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3100

stutter_exit_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3103

stutter_exit_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3107

stutter_exit_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3110

stutter_exit_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3114

stutter_exit_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3118

stutter_entry_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3121

stutter_entry_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3124

stutter_entry_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3128

stutter_entry_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3131

stutter_entry_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3135

stutter_entry_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3138

stutter_entry_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3142

stutter_entry_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3146

urgent_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3149

urgent_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3152

urgent_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3156

urgent_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3159

urgent_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3163

urgent_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3166

urgent_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3170

urgent_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3180

nbp_state_change_watermark[4],bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3183

nbp_state_change_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3186

nbp_state_change_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3191

nbp_state_change_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3194

nbp_state_change_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3198

nbp_state_change_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3201

nbp_state_change_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3205

nbp_state_change_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3211

stutter_exit_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3214

stutter_exit_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3217

stutter_exit_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3221

stutter_exit_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3224

stutter_exit_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3228

stutter_exit_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3231

stutter_exit_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3235

stutter_exit_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3239

stutter_entry_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3242

stutter_entry_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3245

stutter_entry_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3249

stutter_entry_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3252

stutter_entry_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3256

stutter_entry_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3259

stutter_entry_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3263

stutter_entry_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3267

urgent_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3270

urgent_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3273

urgent_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3277

urgent_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3280

urgent_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3284

urgent_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3287

urgent_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3291

urgent_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

330

data->compression_rate[i] = bw_int_to_fixed(vbios->average_compression_rate);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3301

nbp_state_change_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3304

nbp_state_change_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3307

nbp_state_change_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3311

nbp_state_change_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3314

nbp_state_change_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3318

nbp_state_change_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3321

nbp_state_change_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3325

nbp_state_change_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3330

stutter_exit_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3333

stutter_exit_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3336

stutter_exit_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

334

data->compression_rate[i] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3340

stutter_exit_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3343

stutter_exit_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3347

stutter_exit_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3350

stutter_exit_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3354

stutter_exit_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3358

stutter_entry_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3361

stutter_entry_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3364

stutter_entry_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3368

stutter_entry_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3371

stutter_entry_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3375

stutter_entry_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3378

stutter_entry_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3382

stutter_entry_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3386

urgent_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3389

urgent_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3392

urgent_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3396

urgent_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3399

urgent_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3403

urgent_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3406

urgent_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3410

urgent_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

343

data->cursor_width_pixels[i] = bw_int_to_fixed(vbios->cursor_width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3434

nbp_state_change_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3437

nbp_state_change_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3440

nbp_state_change_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3444

nbp_state_change_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3447

nbp_state_change_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3451

nbp_state_change_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3454

nbp_state_change_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3458

nbp_state_change_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3462

stutter_exit_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3465

stutter_exit_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3468

stutter_exit_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3472

stutter_exit_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3475

stutter_exit_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3479

stutter_exit_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3482

stutter_exit_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3486

stutter_exit_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3490

stutter_entry_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3493

stutter_entry_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3496

stutter_entry_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3500

stutter_entry_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3503

stutter_entry_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3507

stutter_entry_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3510

stutter_entry_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3514

stutter_entry_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3518

urgent_watermark[4], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3521

urgent_watermark[5], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3524

urgent_watermark[6], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3528

urgent_watermark[0], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3531

urgent_watermark[1], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3535

urgent_watermark[7], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3538

urgent_watermark[8], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

3542

urgent_watermark[9], bw_int_to_fixed(1000)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

364

data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

365

data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

366

data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

367

data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

368

data->rotation_angle[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

369

data->rotation_angle[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

374

data->compression_rate[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

375

data->compression_rate[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

391

data->h_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

392

data->h_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

393

data->v_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

394

data->v_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

397

data->cursor_width_pixels[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

398

data->cursor_width_pixels[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

417

if (bw_equ(data->h_scale_ratio[i], bw_int_to_fixed(1)) && bw_equ(data->v_scale_ratio[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics && data->stereo_mode[i] == bw_def_mono && data->interlace_mode[i] == 0) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

418

data->h_taps[i] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

419

data->v_taps[i] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

422

data->pitch_in_pixels_after_surface_type[i] = bw_div(data->pitch_in_pixels[i], bw_int_to_fixed(2));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

423

data->src_width_after_surface_type = bw_div(data->src_width[i], bw_int_to_fixed(2));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

424

data->src_height_after_surface_type = bw_div(data->src_height[i], bw_int_to_fixed(2));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

425

data->hsr_after_surface_type = bw_div(data->h_scale_ratio[i], bw_int_to_fixed(2));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

426

data->vsr_after_surface_type = bw_div(data->v_scale_ratio[i], bw_int_to_fixed(2));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

435

if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

450

data->source_height_pixels = bw_mul(bw_int_to_fixed(2), data->src_height_after_rotation);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

452

data->vsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->vsr_after_rotation);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

455

data->source_width_pixels[i] = bw_mul(bw_int_to_fixed(2), data->src_width_after_rotation);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

457

data->hsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->hsr_after_rotation);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

469

data->vsr[i] = bw_mul(data->vsr_after_stereo, bw_int_to_fixed(2));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

475

data->source_width_rounded_up_to_chunks[i] = bw_add(bw_floor2(bw_sub(data->source_width_pixels[i], bw_int_to_fixed(1)), bw_int_to_fixed(128)), bw_int_to_fixed(256));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

478

data->source_width_rounded_up_to_chunks[i] = bw_ceil2(data->source_width_pixels[i], bw_int_to_fixed(128));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

503

if (bw_neq(data->hsr[i], bw_int_to_fixed(1))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

504

if (bw_mtn(data->hsr[i], bw_int_to_fixed(4))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

512

if (dceip->pre_downscaler_enabled == 1 && bw_mtn(data->hsr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

523

if (bw_neq(data->vsr[i], bw_int_to_fixed(1))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

524

if (bw_mtn(data->vsr[i], bw_int_to_fixed(4))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

538

if ((dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1)))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

546

data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875ul, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

549

data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(300234375, 10000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

552

data->lb_line_pitch = bw_ceil2(bw_mul(bw_int_to_fixed(data->lb_bpc[i]), data->source_width_in_lb), bw_int_to_fixed(48));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

555

data->lb_partitions[i] = bw_floor2(bw_div(data->lb_size_per_component[i], data->lb_line_pitch), bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

558

data->lb_partitions_max[i] = bw_int_to_fixed(10);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

561

data->lb_partitions_max[i] = bw_int_to_fixed(7);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

564

if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

571

if (data->enable[i] && data->fbc_en[i] == 1 && (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)) || data->stereo_mode[i] != bw_def_mono || data->bytes_per_pixel[i] != 4)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

578

if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

601

data->dram_efficiency = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

630

if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

665

if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

672

data->bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

673

data->useful_bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

674

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

675

data->latency_hiding_lines[i] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

678

data->bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

679

data->useful_bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

680

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

681

data->latency_hiding_lines[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

684

if (surface_type[i] == bw_def_graphics || (bw_mtn(data->source_width_rounded_up_to_chunks[i], bw_ceil2(data->underlay_maximum_source_efficient_for_tiling, bw_int_to_fixed(256))))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

687

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

688

data->latency_hiding_lines[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

690

data->bytes_per_request[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

691

data->useful_bytes_per_request[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

694

data->bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

695

data->useful_bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

700

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

701

data->latency_hiding_lines[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

702

data->bytes_per_request[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

703

data->useful_bytes_per_request[i] = bw_int_to_fixed(16);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

706

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

707

data->latency_hiding_lines[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

708

data->bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

709

data->useful_bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

713

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

714

data->latency_hiding_lines[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

715

data->bytes_per_request[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

716

data->useful_bytes_per_request[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

719

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

720

data->latency_hiding_lines[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

721

data->bytes_per_request[i] = bw_int_to_fixed(32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

722

data->useful_bytes_per_request[i] = bw_int_to_fixed(16);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

727

data->bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

728

data->useful_bytes_per_request[i] = bw_int_to_fixed(64);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

730

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

731

data->latency_hiding_lines[i] = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

736

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

737

data->latency_hiding_lines[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

740

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

741

data->latency_hiding_lines[i] = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

744

data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

745

data->latency_hiding_lines[i] = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

787

data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc_to_fixed(5, 10)), data->vsr[i]))), bw_int_to_fixed(2)), bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

789

data->v_filter_init[i] = bw_add(data->v_filter_init[i], bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

793

data->v_filter_init[i] = bw_min2(data->v_filter_init[i], bw_int_to_fixed(4));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

799

data->num_lines_at_frame_start = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

802

data->num_lines_at_frame_start = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

804

if ((bw_mtn(data->vsr[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics) || data->panning_and_bezel_adjustment == bw_def_any_lines) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

807

else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

813

data->lb_lines_in_per_line_out_in_beginning_of_frame[i] = bw_div(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->num_lines_at_frame_start);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

815

data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_max2(bw_int_to_fixed(1), data->vsr[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

817

else if (bw_leq(data->vsr[i], bw_int_to_fixed(1))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

818

data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

821

data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(4), bw_int_to_fixed(3));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

824

data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(6), bw_int_to_fixed(4));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

826

else if (bw_leq(data->vsr[i], bw_int_to_fixed(2))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

827

data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

829

else if (bw_leq(data->vsr[i], bw_int_to_fixed(3))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

830

data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(3);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

833

data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(4);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

835

if (data->line_buffer_prefetch[i] == 1 || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(2)) || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(4))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

836

data->horizontal_blank_and_chunk_granularity_factor[i] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

839

data->horizontal_blank_and_chunk_granularity_factor[i] = bw_div(data->h_total[i], (bw_div((bw_add(data->h_total[i], bw_div((bw_sub(data->source_width_pixels[i], bw_int_to_fixed(dceip->chunk_width))), data->hsr[i]))), bw_int_to_fixed(2))));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

841

data->request_bandwidth[i] = bw_div(bw_mul(bw_div(bw_mul(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], data->lb_lines_in_per_line_out_in_middle_of_frame[i]), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), bw_int_to_fixed(data->bytes_per_pixel[i])), data->useful_bytes_per_request[i]), data->lines_interleaved_in_mem_access[i]), data->latency_hiding_lines[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

877

data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_luma_mcifwr_buffer_size);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

880

data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_chroma_mcifwr_buffer_size);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

883

data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

886

data->data_buffer_size[i] = bw_div(bw_int_to_fixed(dceip->underlay_chroma_dmif_size), bw_int_to_fixed(2));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

890

data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

893

data->data_buffer_size[i] = bw_add(bw_int_to_fixed(dceip->underlay_luma_dmif_size), bw_int_to_fixed(dceip->underlay_chroma_dmif_size));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

900

data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

903

data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

909

data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

912

data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

918

data->memory_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

919

data->pipe_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

922

data->memory_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), data->lines_interleaved_in_mem_access[i]), bw_int_to_fixed(data->bytes_per_pixel[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

923

data->pipe_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_int_to_fixed(data->bytes_per_pixel[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

927

data->min_dmif_size_in_time = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

928

data->min_mcifwr_size_in_time = bw_int_to_fixed(9999);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

943

data->total_requests_for_dmif_size = bw_int_to_fixed(0);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

963

data->outstanding_chunk_request_limit[i] = bw_int_to_fixed(127);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

966

data->outstanding_chunk_request_limit[i] = bw_ceil2(bw_div(data->adjusted_data_buffer_size[i], data->pipe_chunk_size_in_bytes[i]), bw_int_to_fixed(1));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

969

data->outstanding_chunk_request_limit[i] = bw_max2(bw_int_to_fixed(127), data->outstanding_chunk_request_limit[i]);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

983

if (data->number_of_displays > 1 || (bw_neq(data->rotation_angle[4], bw_int_to_fixed(0)) && bw_neq(data->rotation_angle[4], bw_int_to_fixed(180)))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

992

data->useful_pte_per_pte_request = bw_int_to_fixed(8);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

993

data->scatter_gather_page_width[i] = bw_div(bw_int_to_fixed(4096), bw_int_to_fixed(data->bytes_per_pixel[i]));

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

994

data->scatter_gather_page_height[i] = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

995

data->scatter_gather_pte_request_rows = bw_int_to_fixed(1);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

996

data->scatter_gather_row_height = bw_int_to_fixed(dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

998

else if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(0)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(180))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

999

data->useful_pte_per_pte_request = bw_int_to_fixed(8);