bus_write_4
bus_write_4(sc->mem_res, offset, val);
bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
bus_write_4(msix->msix_table_res, offset + 8, data);
bus_write_4(msix->msix_table_res, offset, val);
bus_write_4(msix->msix_table_res, offset, val);
bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
bus_write_4(res, offs + EHCI_USBINTR, 0);
bus_write_4(res, offs + XHCI_USBCMD, 0);
bus_write_4(sc->sc_res[0], index * 4, pte);
bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte);
bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte);
bus_write_4(sc->sc_res[0],
bus_write_4(sc->sc_res[0], GFX_FLSH_CNTL, 1);
bus_write_4(sc->sc_res[0], GFX_FLSH_CNTL, 0);
bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2);
bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl);
bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
bus_write_4(sc->sc_iomem, ASMC_MMIO_KEY_NAME, key_int);
bus_write_4(sc->sc_iomem, ASMC_MMIO_KEY_NAME, key_int);
bus_write_4(sc->sc_iomem, ASMC_MMIO_KEY_NAME, idx_val);
bus_write_4(sc->sc_iomem, ASMC_MMIO_KEY_NAME, key_int);
bus_write_4(sc->mem_res, off, val);
bus_write_4(sc->mem_res, off, val);
bus_write_4(sc->mem_res[slot->num], off, val);
#define OUTL_OFF(o, v) bus_write_4(np->io_res, (o), (v))
#define OUTL_OFF(o, v) bus_write_4(np->mmio_res, (o), (v))
bus_write_4(adev->rio_mem, (mmMM_INDEX * 4), (reg * 4));
bus_write_4(adev->rio_mem, (reg * 4), v);
bus_write_4(adev->rio_mem, (mmMM_INDEX * 4), (reg * 4));
bus_write_4(adev->rio_mem, (mmMM_DATA * 4), v);
bus_write_4(sc->res_ctrl, 0, val);
bus_write_4(sc->res_count, 0, val);
bus_write_4((sc)->tco_res, (off), (val))
bus_write_4((sc)->smi_res, (off), (val))
bus_write_4((sc)->gcs_res, (off), (val))
bus_write_4(sc->bge_res2, reg, val)
bus_write_4(sc->bnx_res2, reg, val)
#define TWE_CONTROL(sc, val) bus_write_4((sc)->twe_io, 0x0, (u_int32_t)val)
#define TWE_COMMAND_QUEUE(sc, val) bus_write_4((sc)->twe_io, 0x8, (u_int32_t)val)
#define vtmmio_write_config_4(sc, o, v) bus_write_4((sc)->res[0], (o), (v))
#define vtpci_write_config_4(sc, o, v) bus_write_4((sc)->vtpci_res, (o), (v))
bus_write_4(sc->mm_res, offset, val);