bus_write_1
bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
bus_write_1(res, eecp + XHCI_XECP_BIOS_SEM, 0x00);
(bus_write_1(amdsmb->res, register, value))
bus_write_1(sc->io_res, ICH_HST_STA, 0xff);
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CMD, byte);
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_D0, byte);
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_D0, word & 0xff);
bus_write_1(sc->io_res, ICH_D1, word >> 8);
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_D0, sdata & 0xff);
bus_write_1(sc->io_res, ICH_D1, sdata >> 8);
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_D0, count);
bus_write_1(sc->io_res, ICH_BLOCK_DB, buf[0]);
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_D0, *count); /* XXX? */
bus_write_1(sc->io_res, ICH_HST_CNT,
bus_write_1(sc->io_res,
bus_write_1(sc->io_res,
bus_write_1(sc->io_res,
bus_write_1(sc->io_res,
bus_write_1(sc->io_res, ICH_HST_STA, status);
#define ASMC_DATAPORT_WRITE(sc, val) bus_write_1(sc->sc_ioport, 0x00, val)
#define ASMC_CMDPORT_WRITE(sc, val) bus_write_1(sc->sc_ioport, 0x04, val)
bus_write_1(sc->sc_iomem, ASMC_MMIO_DATA + i, buf[i]);
bus_write_1(sc->sc_iomem, ASMC_MMIO_DATA_LEN, len);
bus_write_1(sc->sc_iomem, ASMC_MMIO_SMC_ID, 0);
bus_write_1(sc->sc_iomem, ASMC_MMIO_CMD, ASMC_CMDWRITE);
bus_write_1(sc->sc_iomem, ASMC_MMIO_STATUS, 0);
bus_write_1(sc->sc_iomem, ASMC_MMIO_SMC_ID, 0);
bus_write_1(sc->sc_iomem, ASMC_MMIO_CMD, ASMC_CMDGETINFO);
bus_write_1(sc->sc_iomem, ASMC_MMIO_STATUS, 0);
bus_write_1(sc->sc_iomem, ASMC_MMIO_SMC_ID, 0);
bus_write_1(sc->sc_iomem, ASMC_MMIO_CMD, ASMC_CMDGETBYINDEX);
bus_write_1(sc->sc_iomem, ASMC_MMIO_STATUS, 0);
bus_write_1(sc->sc_iomem, ASMC_MMIO_SMC_ID, 0);
bus_write_1(sc->sc_iomem, ASMC_MMIO_CMD, ASMC_CMDREAD);
bus_write_1(sc->sc_iomem, ASMC_MMIO_STATUS, 0);
bus_write_1(sc->mem_res, off, val);
bus_write_1((bt)->port, reg, value)
bus_write_1(sc->mem_res, off, val);
bus_write_1(sc->mem_res[slot->num], off, val);
#define OUTB_OFF(o, v) bus_write_1(np->io_res, (o), (v))
#define OUTB_OFF(o, v) bus_write_1(np->mmio_res, (o), (v))
bus_write_1(res, 0, reg); /* Index */
bus_write_1(res, 0, reg); /* Index */
bus_write_1(res, 1, val); /* Data */
bus_write_1(pmres, AMDFCH41_PM_DECODE_EN0, val);
bus_write_1(pmres, AMDFCH41_PM_DECODE_EN3, val);
bus_write_1((sc)->tco_res, (off), (val))
bus_write_1((sc)->ipmi_io_res[0], (sc)->ipmi_io_spacing * (x), value)
bus_write_1((sc)->ipmi_io_res[(x)], 0, value)
(bus_write_1(amdpm->res, register, value))
bus_write_1(res, 0, reg); /* Index */
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff);
bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
#define vtmmio_write_config_1(sc, o, v) bus_write_1((sc)->res[0], (o), (v))
#define vtpci_write_config_1(sc, o, v) bus_write_1((sc)->vtpci_res, (o), (v))